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參數(shù)資料
| 型號(hào)： | AD7225LR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | DAC |
| 英文描述： | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| 中文描述： | PARALLEL, 8 BITS INPUT LOADING, 8-BIT DAC, PDSO24 |
| 封裝： | ROHS COMPLIANT, MS-013AD, SOIC-24 |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 339K |
| 代理商： | AD7225LR |
AD7225
REV. B
–6–
CIRCUIT INFORMAT ION
D/A SE CT ION
T he AD7225 contains four, identical, 8-bit voltage mode
digital-to-analog converters. Each D/A converter has a separate
reference input. T he output voltages from the converters have
the same polarity as the reference voltages, allowing single sup-
ply operation. A novel DAC switch pair arrangement on the
AD7225 allows a reference voltage range from +2 V to +12.5 V
on each reference input.
Each DAC consists of a highly stable, thin-film, R-2R ladder
and eight high speed NMOS, single-pole, double-throw
switches. T he simplified circuit diagram for channel A is shown
in Figure 7. Note that AGND (Pin 6) is common to all four
DACs.
Figure 7. D/A Simplified Circuit Diagram
T he input impedance at any of the reference inputs is code de-
pendent and can vary from 11 k
minimum to infinity. T he
lowest input impedance at any reference input occurs when that
DAC is loaded with the digital code 01010101. T herefore, it is
important that the reference presents a low output impedance
under changing load conditions. T he nodal capacitance at the
reference terminals is also code dependent and typically varies
from 15 pF to 35 pF.
Each V
OUT
pin can be considered as a digitally programmable
voltage source with an output voltage of:
V
OUT X
= D
X
V
REFX
where D
X
is fractional representation of the digital input code
and can vary from 0 to 255/256.
T he output impedance is that of the output buffer amplifier.
OP-AMP SE CT ION
Each voltage mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is ca-
pable of developing +10 V across a 2 k
load and can drive ca-
pacitive loads of 3300 pF.
T he AD7225 can be operated single or dual supply; operating
with dual supplies results in enhanced performance in some pa-
rameters which cannot be achieved with single supply operation.
In single supply operation (V
SS
= 0 V = AGND) the sink capa-
bility of the amplifier, which is normally 400
μ
A, is reduced as
the output voltage nears AGND. T he full sink capability of
400
μ
A is maintained over the full output voltage range by tying
V
SS
to –5 V. T his is indicated in Figure 8.
Settling-time for negative-going output signals approaching
AGND is similarly affected by V
SS
. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by V
SS
.
Figure 8. Variation of I
SINK
with V
OUT
Additionally, the negative V
SS
gives more headroom to the out-
put amplifiers which results in better zero code performance and
improved slew rate at the output, than can be obtained in the
single supply mode.
DIGIT AL SE CT ION
T he AD7225 digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. T o minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (V
DD
and DGND) as practi-
cally possible.
INT E RFACE LOGIC INFORMAT ION
T he AD7225 contains two registers per DAC, an input register
and a DAC register. Address lines A0 and A1 select which input
register will accept data from the input port. When the
WR
sig-
nal is LOW, the input latches of the selected DAC are transpar-
ent. T he data is latched into the addressed input register on the
rising edge of
WR
. T able I shows the addressing for the input
registers on the AD7225.
T able I. AD7225 Addressing
A1
A0
Selected Input Register
L
L
H
H
L
H
L
H
DAC A Input Register
DAC B Input Register
DAC C Input Register
DAC D Input Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7225 | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7225BQ | ECONOLINE: REC2.2-S_DRW(Z)/H* - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- 4.5-9V, 9-18V, 18-36V, 36-72V Wide Input Range 2 : 1- UL94V-0 Package Material- Continuous Short Circiut Protection- Cost Effective- 100% Burned In- Efficiency to 84% |
| AD7225CQ | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| AD7225LP | LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
| AD7226 | LC2MOS Quad 8-Bit D/A Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7225LR-REEL | 制造商:Analog Devices 功能描述:DAC 4-CH R-2R 8-bit 24-Pin SOIC W T/R |
| AD7225LRZ | 功能描述:IC DAC 8BIT QUAD W/AMP 24SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7225LRZ-REEL | 功能描述:IC DAC 8BIT QUAD W/AMP 24SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD7225TCHIPS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Digital-to-Analog Converter |
| AD7225TE | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Quad 8-Bit DAC with Separate Reference Inputs |
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