參數(shù)資料
型號: AD7143ACPZ-1500RL7
廠商: Analog Devices Inc
文件頁數(shù): 39/57頁
文件大?。?/td> 0K
描述: IC CTLR PROGRAMMABLE CDC 16LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 電容數(shù)字轉(zhuǎn)換器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 1mA
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
其它名稱: AD7143ACPZ-1500RL7DKR
AD7143
Rev. 0 | Page 43 of 56
BANK 2 REGISTERS
All address values are expressed in hexadecimal format.
Table 30. STAGE0 Configuration Registers
Address
Data Bit
Default
Type
Name
Description
0x080
[15:0]
X
R/W
STAGE0_CONNECTION[6:0]
STAGE0 CIN(6:0) connection setup (see Table 38)
0x081
[15:0]
X
R/W
STAGE0_CONNECTION 7
STAGE0 CIN7 connection setup (see Table 39)
0x082
[15:0]
X
R/W
STAGE0_AFE_OFFSET
STAGE0 AFE offset control (see Table 40)
0x083
[15:0]
X
R/W
STAGE0_SENSITIVITY
STAGE0 sensitivity control (see Table 41)
0x084
[15:0]
X
R/W
STAGE0_OFFSET_LOW
STAGE0 initial offset low value
0x085
[15:0]
X
R/W
STAGE0_OFFSET_HIGH
STAGE0 initial offset high value
0x086
[15:0]
X
R/W
STAGE0_OFFSET_HIGH_CLAMP
STAGE0 offset high clamp value
0x087
[15:0]
X
R/W
STAGE0_OFFSET_LOW_CLAMP
STAGE0 offset low clamp value
Table 31. STAGE1 Configuration Registers
Address
Data Bit
Default
Type
Name
Description
0x088
[15:0]
X
R/W
STAGE1_CONNECTION[6:0]
STAGE1 CIN(6:0) connection setup (see Table 38)
0x089
[15:0]
X
R/W
STAGE1_CONNECTION 7
STAGE1 CIN7 connection setup (see Table 39)
0x08A
[15:0]
X
R/W
STAGE1_AFE_OFFSET
STAGE1 AFE offset control (see Table 40)
0x08B
[15:0]
X
R/W
STAGE1_SENSITIVITY
STAGE1 sensitivity control (see Table 41)
0x08C
[15:0]
X
R/W
STAGE1_OFFSET_LOW
STAGE1 initial offset low value
0x08D
[15:0]
X
R/W
STAGE1_OFFSET_HIGH
STAGE1 initial offset high value
0x08E
[15:0]
X
R/W
STAGE1_OFFSET_HIGH_CLAMP
STAGE1 offset high clamp value
0x08F
[15:0]
X
R/W
STAGE1_OFFSET_LOW_CLAMP
STAGE1 offset low clamp value
Table 32. STAGE2 Configuration Registers
Address
Data Bit
Default
Type
Name
Description
0x090
[15:0]
X
R/W
STAGE2_CONNECTION[6:0]
STAGE2 CIN(6:0) connection setup (see Table 38)
0x091
[15:0]
X
R/W
STAGE2_CONNECTION 7
STAGE2 CIN7 connection setup (see Table 39)
0x092
[15:0]
X
R/W
STAGE2_AFE_OFFSET
STAGE2 AFE offset control (see Table 40)
0x093
[15:0]
X
R/W
STAGE2_SENSITIVITY
STAGE2 sensitivity control (see Table 41)
0x094
[15:0]
X
R/W
STAGE2_OFFSET_LOW
STAGE2 initial offset low value
0x095
[15:0]
X
R/W
STAGE2_OFFSET_HIGH
STAGE2 initial offset high value
0x096
[15:0]
X
R/W
STAGE2_OFFSET_HIGH_CLAMP
STAGE2 offset high clamp value
0x097
[15:0]
X
R/W
STAGE2_OFFSET_LOW_CLAMP
STAGE2 offset low clamp value
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