參數(shù)資料
型號: AD7143ACPZ-1500RL7
廠商: Analog Devices Inc
文件頁數(shù): 35/57頁
文件大?。?/td> 0K
描述: IC CTLR PROGRAMMABLE CDC 16LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: 電容數(shù)字轉(zhuǎn)換器
輸入類型: 邏輯
輸出類型: 邏輯
接口: I²C
電流 - 電源: 1mA
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 16-LFCSP-VQ
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 781 (CN2011-ZH PDF)
其它名稱: AD7143ACPZ-1500RL7DKR
AD7143
Rev. 0 | Page 39 of 56
Table 22. STAGE_HIGH_INT_EN Register
Address
Data Bit
Default
Type
Name
Description
[0]
0
STAGE0_HIGH_INT_EN
STAGE0 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[1]
0
STAGE1_HIGH_INT_EN
STAGE1 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[2]
0
STAGE2_HIGH_INT_EN
STAGE2 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[3]
0
STAGE3_HIGH_INT_EN
STAGE3 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[4]
0
STAGE4_HIGH_INT_EN
STAGE4 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[5]
0
STAGE5_HIGH_INT_EN
STAGE5 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[6]
0
STAGE6_HIGH_INT_EN
STAGE6 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
[7]
0
STAGE7_HIGH_INT_EN
STAGE7 high interrupt enable
0 = interrupt source disabled
1 = INT asserted if STAGE0 high threshold is exceeded
0x006
[15:8]
R/W
Unused
Set unused register bits = 0
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