參數(shù)資料
型號(hào)： AD7008JP50
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： CMOS DDS Modulator
中文描述： 1-BIT, DSP-NUM CONTROLLED OSCILLATOR, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 16/16頁(yè)
文件大小： 505K
代理商： AD7008JP50
REV. B
–16–
AD7008
A 3.5" floppy disk containing software to control the AD7008 is
provided with the AD7008/PCB. This software was developed
using C. The C source code is provided in a file named
A:\AD7008.C, which the user may view, run, or modify.
An executable version of this software is also provided, and can
be executed from DOS by typing “A:\AD7008.” The software
prompts the user to provide the necessary information needed
by the program. Additional information is included in a test file
named A:\readme.txt.
A windows 3.1 executable called WIN7008 is also included.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Pin PLCC (P-44A)
6
IDPIN 1
7
40
39
17
18
29
28
TOP VIEW
(PINS DOWN)
0.695 (17.65)
0.656 (16.66)
0.048 (1.21)
0.042 (1.07)
0.048 (1.21)
0.042 (1.07)
0.020
(0.50)
R
0.021 (0.53)
0.013 (0.33)
0.050
(1.27)
BSC
0.63 (16.00)
0.59 (14.99)
0.032 (0.81)
0.026 (0.66)
0.180 (4.57)
0.165 (4.19)
0.040 (1.01)
0.025 (0.64)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
0.110 (2.79)
0.085 (2.16)
INPUTS/OUTPUTS
Name
Description
P1
36-pin edge connector to connect to parallel
port of PC.
CMOS input for clock R6 provides termination.
CMOS input to select between Freq0 and Freq 1.
Low selects Freq 0.
CMOS input for serial input pin.
CMOS input for clocking in SDATA.
Analog output.
Complementary analog output.
Test point for V
REF
pin.
+5 V and ground power connection.
External sleep command input.
CLOCK
FSEL
SDATA
SCLK
I
OUT
I
OUT
N
V
REF
P2
LK1
Figure 36.
Controlling the AD7008/PCB
The AD7008/PCB is designed to allow control (frequency
specification, reset, etc.) through the parallel printer port of a
standard IBM-compatible PC. The user simply disconnects the
printer cable from the printer and inserts it into edge connector
P1 of the evaluation board.
The printer port provides information to the AD7008/PCB
through eight data lines and four control lines. Control signals
are latched on the AD7008/PCB to prevent problems with long
printer cables.
P
C
V
CC
OUT
V
EE
+5V
14
7
XTAL1
8
C9
0.1μF
PR
Q
Q
CL
C
D
>
PRQ
Q
CL
C
D
>
LATCH
LOAD
2
3
4
5
6
8
9
10
11
12
13
1
LLOAD
WR
+5V
+5V
+5V
U2
74HC74
L
WR
U2
74HC74
C36DRPF
P1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
LATCH
D0
D1
D2
D3
D4
D5
D6
D7
RESET
LOAD
WR
2
3
4
5
6
7
8
9
10
D0
D1
D2
D3
D4
D5
D6
D7
10k
10PB+5
RZ1
2
3
4
5
6
LATCH
RESET
LOAD
WR
4.7k
6RZ2
DUU1
6
5
2
1
4
3
17
28
39
44
7
18
29
43
40
V
REF
COMP
FSADJUST
19
20
21
22
23
24
25
26
8
9
10
11
12
13
14
15
16
27
32
33
34
35
36
41
42
31
30
38
37
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
RESET
SLEEP
1
2
3
H3M
LK1
+5V
GND
+5V
+5VD
1
2
P2
PCTB2
D15
WR
CS
TC0
TC1
R1
10k
SMB
SCLK
R2
10k
R3
SMB
R6
50
OPTIONAL
TC2
TC3
SCLK
FSELECT
CLK
D0
D1
D2
D3
LLOAD
RESET
DGND
DGND
DGND
DGND
AGND
TEST
+5V
+5V
+5V
+5V
C7
0.1μF
+5V
R4
50
SMB
I
OUT
FSADJ
390
L
WR
SMB
SMB
I
OUT
I
OUT
V
REF
SMB
I
OUT
R5
50
C6
0.1μF
C2
0.1μF
C3
0.1μF
C4
0.1μF
C5
0.1μF
C1
C8
D0
D1
D2
D3
D4
D5
D6
D7
V
AA
V
DD
V
DD
V
DD
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