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參數(shù)資料
| 型號： | AD6654BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 75/88頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 標準包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應商設備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD6654
Rev. 0 | Page 77 of 88
<10>: ADC Port CLK Invert Bit. When this bit is set, the
inverted ADC port clock is used to register ADC input data into
the part. When this bit is cleared, the clock is used as is, without
any inversion or phase change.
<9>: Reserved. This bit must be written with Logic 0.
<8>: Reserved. This bit must be written with Logic 0.
<7:6>: ADC Pre PLL Clock Divider Bits.: These bits control the
PLL clock divider. The PLL clock is derived from the ADC data
port CLK.
Table 31. Divide-by Values for PLL Clock Divider Bits
PLL Clock Divider Bits <12:11>
Divide-by Value
00
Divide by 1, bypass
01
Divide by 2
10
Divide by 4
11
Divide by 8
<5:1>: PLL Clock Multiplier Bits. These bits control the PLL
clock multiplier. The output of the PLL clock divider is
multiplied with the binary value of these bits. Valid range for
the multiplier is from 4 to 20. A value outside this range powers
down the PLL, resulting in the PLL clock being the same as the
ADC data port CLK.
<0>: This bit is open.
ADC Port Gain Control <7:0>
<7>: This bit is open.
<6:1>: This 6-bit word specifies the relinearization pipe delay to
be used in the ADC input gain control block. The decimal
representation of these bits is the number of input clock cycle
pipeline delays between the external EXP data output and the
internal application of relinearization based on EXP.
<0>: Gain Control Enable Bit. This bit controls the configura-
tion of the EXP<2:0> bits for the ADC input port. When the
gain control enable bit is Logic 1, the EXP<2:0> bits are
configured as outputs. When this bit is cleared, the EXP<2:0>
bits are inputs.
ADC Port Dwell Timer <19:0>
This register is used to set the dwell time for the gain control
block. When the gain control block is active and detects a
decrease in the signal level below the lower threshold value
(programmable), a dwell-time counter is initiated to provide
temporal hysteresis. Doing so prevents the gain from being
continuously switched. Note that the dwell timer is turned on
only after a drop below the lower threshold is detected in the
signal level.
ADC Port Power Monitor Period <23:0>
This register is used in the power monitoring logic to set the
period of time for which ADC input data is monitored. This
value represents the monitor period in number of ADC port
clock cycles.
ADC Port Power Monitor Output <23:0>
This register is read only and contains the current status of the
power monitoring logic output. The output is dependent on the
power monitoring mode selected. When the power monitor
block is enabled, this register is updated at the end of each
power monitor period. This register is updated even if an
interrupt signal is not generated.
ADC Port Upper Threshold <9:0>
This register serves the dual purpose of specifying the upper
threshold value in the gain control block and in the power
monitoring block, depending on which block is active. ADC
port input data having a magnitude greater than this value
triggers a gain change in the gain control block. ADC port input
data having a magnitude greater than this value is monitored in
the power monitoring block (in peak detect or threshold
crossing mode). The value of the register is compared with the
absolute magnitude of the input port data.
ADC Port Lower Threshold <9:0>
This register is used in the gain control block and represents the
magnitude of the lower threshold for ADC port input data. Any
ADC input data having a magnitude below the lower threshold
initiates the dwell time counter. The value of the register is
compared with the absolute magnitude of the input port data.
ADC Port Signal Monitor <4:0>
This register controls the functions of the power monitoring
block.
<4>: Disable Power Monitor Period Timer Bit. When this bit is
set, the power monitor period timer no longer controls the
update of the power monitor holding register. A user read to the
power monitor holding register updates this register. When this
bit is cleared, the power monitor period register controls the
timer and, therefore, controls the update rate of the power
monitor holding register.
<3>: Clear-on-Read Bit. When this bit is set, the power monitor
holding register is cleared every time this register is read. This
bit controls whether the power monitoring function is cleared
after a read of the power monitor period register. If this bit is
set, the monitoring function is cleared after the read. If this bit
is Logic 0, the monitoring function is not cleared. This bit is a
don’t care bit, if the disable integration counter bit is cleared.
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| AD6654CBC | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD6654CBCZ | 功能描述:IC ADC 14BIT W/4CH RSP 256CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:250 系列:- 位數(shù):12 采樣率（每秒）:1.8M 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:1.82W 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應商設備封裝:48-LQFP（7x7） 包裝:管件 輸入數(shù)目和類型:2 個單端，單極 |
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關產品:- 已供物品:模塊 其它名稱:SER3796 |
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