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| 型號： | AD6654BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT W/6CH RSP 256CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 92.16M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 256-CSPBGA（17x17） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD6654
Rev. 0 | Page 31 of 88
ADC INPUT PORT MONITOR FUNCTION
The AD6654 provides a power monitor function that can
monitor the DDC input stream and gather statistics about the
received signal in a signal chain. This function block can
operate in one of three modes measuring the following over a
programmable period of time:
Peak power
Mean power
Number of samples crossing a threshold
These functions are controlled via the 2-bit power monitor
function select bits in the power monitor control register of the
DDC input port. The DDC input port can be set for different
modes, but only one function can be active at a time. The three
modes of operation can function continuously over a program-
mable time period. This time period is programmed as the
number of input clock cycles in a 24-bit ADC monitor period
register (AMPR). An internal magnitude storage register (MSR)
is used to monitor, accumulate, or count, depending on the
mode of operation.
PEAK DETECTOR MODE
Control Bits 00
The magnitude of the input port signal is monitored over a
programmable time period (given by AMPR) to give the peak
value detected. This mode is set by programming Logic 0 in the
power monitor function select bits in the power monitor
control register of the DDC input port. The 24-bit AMPR must
be programmed before activating this mode.
After enabling this mode, the value in the AMPR is loaded into
a monitor period timer and the countdown is started. The
magnitude of the input signal is compared to the MSR, and the
greater of the two is updated back into the MSR. The initial
value of the MSR is set to the current ADC input signal magni-
tude. This comparison continues until the monitor period timer
reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power monitor holding register,
which can be read through the microport or the serial port. The
monitor period timer is reloaded with the value in the AMPR,
and the countdown is started. Also, the magnitude of the first
input sample is updated in the MSR, and the comparison and
update procedure, as explained above, continues. If the
interrupt is enabled, an interrupt is generated, and the interrupt
status register is updated when the AMPR reaches a count of 1.
Figure 44 is a block diagram of the peak detector logic. The
MSR contains the absolute magnitude of the peak detected by
the peak detector logic.
POWER MONITOR
HOLDING
REGISTER
MAGNITUDE
STORAGE
REGISTER
COMPARE
A
> B
TO
MEMORY
MAP
FROM
MEMORY
MAP
FROM
INPUT
PORTS
LOAD
CLEAR
LOAD
05156-033
IS COUNT = 1?
DOWN
COUNTER
TO
INTERRUPT
CONTROLLER
POWER MONITOR
PERIOD REGISTER
Figure 44. ADC Input Peak Detector Block Diagram
MEAN POWER MODE
Control Bits 01
In this mode, the magnitude of the input port signal is
integrated (by adding an accumulator) over a programmable
time period (given by AMPR) to give the integrated magnitude
of the input signal. This mode is set by programming Logic 1 in
the power monitor function select bits in the power monitor
control register of the DDC input port. The 24-bit AMPR,
representing the period over which integration is performed,
must be programmed before activating this mode.
After enabling this mode, the value in the AMPR is loaded into
a monitor period timer, and the countdown is immediately
started. The 15-bit magnitude of input signal is right-shifted by
nine bits to give 6-bit data. This 6-bit data is added to the
contents of a 24-bit holding register, thereby performing an
accumulation. The integration continues until the monitor
period timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power monitor holding register
(after some formatting), which can be read through the micro-
port or the serial port. The monitor period timer is reloaded
with the value in the AMPR, and the countdown is started.
Also, the first input sample signal magnitude is updated in the
MSR, and the accumulation continues with the subsequent
input samples. If the interrupt is enabled, an interrupt is
generated, and the interrupt status register is updated when the
AMPR reaches a count of 1. Figure 45 illustrates the mean
power monitoring logic.
The value in the MSR is a floating-point number with 4 MSBs
and 20 LSBs. If the 4 MSBs are EXP and the 20 LSBs are MAG,
the value in dBFS can be decoded using the following equation:
()
=
1
2
log
10
20
EXP
MAG
MeanPower
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