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參數(shù)資料
| 型號： | AD6652BC |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| 中文描述： | 12位，65 MSPS的IF到基帶分集接收機 |
| 文件頁數(shù)： | 26/76頁 |
| 文件大?。?/td> | 1839K |
| 代理商： | AD6652BC |
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AD6652
Internal Reference Connection
A comparator within the AD6
SENSE pin and configures t
states, which are summarized in Table 11. If SENSE is grounde
the reference amplifier switch is connected to the internal
resistor divider (see Figure 40), setting VREF to a FIXED 1 V
reference output. Connecting the SENSE pin directly to V
switches the reference amplifier output to the SENSE pin,
completing the loop and providing a fixed 0.5 V reference
output. If a resistor divider is connected, as shown in Figure 41,
the switch is again set to the SENSE pin. This puts the reference
amplifier in a noninverting mode with the VREF programmab
output defined as follows:
Rev. 0 | Page 26 of 76
he reference into four possible
d,
REF
le
ce configurations, REFT and REFB drive the A/D
put span. The input range of
oltage at the reference pin for
the ADC always equals twice the v
either an internal or an external reference.
d
re not
shown.
lting VREF
Resu
External Reference
0.5
0.5 × (1 + R2/R1)
1.0
652 detects the potential at the
In all referen
conversion core and establish its in
VREF
= 0.5 × (1 +
R
2/
R
1)
The reference amplifier switch is located near the bottom left.
The SENSE pin is shown connected to ground, which sets VREF
to 1 V. Decoupling capacitors must be duplicated for the
Channel B ADC core, if it is used. The Channel B ref amp an
ADC core are identical to those of Channel A, but a
Table 11. Reference SENSE Operation
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
Internal Fixed Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
AGND to 0.2 V
(V)
Resulting Differential Span (V p-p)
2 × External Reference
1.0
2 × VREF (See Figure 42)
2.0
0
VINA+
VINA–
REFT_A
VREF
VREF
TO CH B
REF AMP
SELECT
LOGIC
CORE
REFB_A
0.5V
0.1
μ
F
SENSE
CH A
ADC
0.1
μ
F
REF
AMP A
0.1
μ
F
10
μ
F
R
INT
0.1
μ
F
10
μ
F
R
INT
Figure 40. Fixed Internal Reference Configuration
0
VINA+
VINA–
REFT_A
VREF
TO CH B
REF AMP
REF
AMP A
CH A
ADC
CORE
REFB_A
0.1
μ
F
0.1
μ
F
μ
10
μ
VREF
0.5V
0.1 F
0.1
μ
F
F
10
μ
F
R
INT
SENSE
SELECT
R
INT
R2
R1
WHERE R1 + R2 =
10k
TO 20k
Figure 41. Programmable Reference Configuration
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD6652BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board With AD6652 And Software |
| AD6652BC/PCBZ | 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHA 制造商:Analog Devices 功能描述:DUAL CHANNEL ADC WITH QUAD CHANNEL RSP - Bulk |
| AD6652PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 65 MSPS IF to Baseband Diversity Receiver |
| AD6652XBC | 制造商:Analog Devices 功能描述:- Bulk |
| AD6653 | 制造商:AD 制造商全稱:Analog Devices 功能描述:IF Diversity Receiver |
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