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參數資料
| 型號： | AD6624AS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網絡 |
| 英文描述： | Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP128 |
| 封裝： | PLASTIC, MQFP-128 |
| 文件頁數： | 5/40頁 |
| 文件大?。?/td> | 506K |
| 代理商： | AD6624AS |
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REV. B
–5–
AD6624
MICROPROCESSOR PORT TIMING CHARACTERISTICS
1, 2
Test
Level
AD6624AS
Typ
Parameter (Conditions)
Temp
Min
Max
Unit
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM Write Timing
:
t
SC
t
HC
t
HWR
t
SAM
t
HAM
t
DRDY
t
ACC
MODE INM Read Timing
:
t
SC
t
HC
t
SAM
t
HAM
t
DRDY
t
ACC
MICROPROCESSOR PORT, MODE MNM (MODE = 1)
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
WR(
RW
)
to RDY(
DTACK
) Hold Time
Address/Data to
WR
(RW) Setup Time
Address/Data to RDY(
DTACK
) Hold Time
WR
(RW) to RDY(
DTACK
) Delay
WR
(RW) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
5.5
1.0
8.0
–0.5
7.0
4.0
4
×
t
CLK
ns
ns
ns
ns
ns
ns
ns
5
×
t
CLK
9
×
t
CLK
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
Address to
RD
(
DS
) Setup Time
Address to Data Hold Time
RD
(
DS
) to RDY(
DTACK
) Delay
RD
(
DS
) to RDY(
DTACK
) High Delay
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
4.0
2.0
0.0
7.0
4.0
8
×
t
CLK
ns
ns
ns
ns
ns
ns
10
×
t
CLK
13
×
t
CLK
MODE MNM Write Timing
:
t
SC
t
HC
t
HDS
t
HRW
t
SAM
t
HAM
t
ACC
MODE MNM Read Timing
:
t
SC
t
HC
t
SAM
t
HAM
t
ZD
t
ACC
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
DS
(
RD
) to
DTACK
(RDY) Hold Time
RW(
WR
) to
DTACK
(RDY) Hold Time
Address/Data to RW(
WR
) Setup Time
Address/Data to RW(
WR
) Hold Time
RW(
WR
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
5.5
1.0
8.0
8.0
–0.5
7.0
4
×
t
CLK
ns
ns
ns
ns
ns
ns
ns
5
×
t
CLK
9
×
t
CLK
Control
3
to
↑
CLK Setup Time
Control
3
to
↑
CLK Hold Time
Address to
DS
(
RD
) Setup Time
Address to Data Hold Time
Data Three-State Delay
DS
(
RD
) to
DTACK
(RDY) Low Delay
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
4.0
2.0
8.0
0.0
7.0
8
×
t
CLK
ns
ns
ns
ns
ns
ns
10
×
t
CLK
13
×
t
CLK
NOTES
1
All timing specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2
C
LOAD
= 40 pF on all outputs unless otherwise specified.
3
Specification pertains to control signals: RW, (
WR
),
DS
, (
RD
),
CS
.
Specifications subject to change without notice.
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相關代理商/技術參數 |
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| AD662BQ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12-Bit Digital-to-Analog Converter |
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