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參數(shù)資料
| 型號(hào)： | AD6623PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，104 MSPS的數(shù)字傳輸信號(hào)處理器判刑 |
| 文件頁數(shù)： | 35/40頁 |
| 文件大?。?/td> | 381K |
| 代理商： | AD6623PCB |
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REV. 0
AD6623
–35–
Bit 6
Can be set through the serial port (see section on
serial word formats).
Sets (N
RCF
/L
RCF
)
–
1
(0xn0D) Channel Mode Control 2
Bits 7
–
6:
Sets the RCF Coarse Scale as shown in Table XXIII.
Bits 3
–
0:
Table XXIII. RCF Coarse Scale
Bit 7
Bit 6
RCF Coarse Scale (dB)
0
0
1
1
0
1
0
1
0
–
6
–
12
–
18
Bit 5:
Bits 4
–
0:
High enables the RCF phase equalizer.
Sets the serial clock divider (SDIV) that determines the
serial clock frequency based on the following equation.
f
CLK
SDIV
SCLK
=
+
1
(28)
(0xn0E) Fine Scale Factor
Bits 15
–
2:
Sets the RCF Fine Scale Factor as an unsigned number
representing the values (0,2). This register is shad-
owed for synchronization purposes. The shadow can
be read back directly, the Fine Scale Factor can not.
Bits 1
–
0:
Reserved.
(0xn0F) RCF Time Slot Hold-Off Counter
Bits 17
–
16: The Time Slot Sync Select bits are used to set which
sync pin will initiate a time slot sync sequence.
Bits 15
–
0:
The Hold-Off Counter is used to synchronize the
change of RCF Fine Scale. See the Synchronization
section for a detailed explanation. If no synchroniza-
tion is required, this register should be set to 0.
(0xn10–0xn11) RCF Phase Equalizer Coefficients
See the RCF section for details.
(0xn12–0xn15) FIR-PSK Magnitudes
See the RCF section for details.
(0xn16) Serial Port Setup
Bits 7
–
6:
Serial Data Frame Start Select
Title XXIV. Serial Port Setup
Bit 7
Bit 6
Serial Data Frame Start
0
1
1
X
0
1
Internal Frame Request
External SDFI Pad
Previous Channel
’
s Frame End
Bit 5:
High means SDFO is a frame end, low means SDFO
is a frame request.
High selects serial slave mode. SCLK is an input in
serial slave mode.
High enables Fine Scaling through the Serial Port
(not available in FIR Mode).
High enables Serial Time Slot Syncs (not available
in FIR Mode).
High enables Power Ramp coefficient interpolation.
High enables the Power Ramp.
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
(0xn17) Power Ramp Length 0
This is the length of the ramp for mode 0, minus one.
(0xn18) Power Ramp Length 1
This is the length of the ramp for mode 1, minus one. Setting
this to zero disables dual ramps.
(0xn19) Power Ramp Rest Time
This is the number of RCF output samples to rest for between a
ramp down and a ramp up.
(0xn1A–0xn1F) Unused
(0xn20–0xn3F) Data Memory
This group of registers contain the RCF Filter Data. See the RCF
section for additional details.
(0xn40–0xn17F) Power Ramp Coefficient Memory
This group of registers contain the Power Ramp Coefficients.
See the Power Ramp section for additional details.
(0xn80–0xn1FF) Coefficient Memory
This group of registers contain the RCF Filter Coefficients.
See the RCF section for additional details.
PSEUDOCODE
Write Pseudocode
Void Write_Micro(ext_address, int data);
Main()
{
/* This code shows the programming of the
NCO frequency register using the Write_Micro
function defined above. The variable
address is the External Address A[2:0] and
data is the value to be placed in the
external interface register.
Internal Address = 0x102, channel 1
*/
/*Holding registers for NCO byte wide
access data*/
int d3, d2, d1, d0;
/*NCO frequency word (32 bits wide)*/
NCO_FREQ=0x1BEFEFFF;
/*write Chan */
Write_Micro(7, 0x01);
/*write Addr */
Write_Micro(6,0x02);
/*write Byte 3*/
d3=(NCO_FREQ & 0xFF02Y
∞
00)>>24;
Write_Micro(3,d3);
/*write Byte 2*/
d2=(NCO_FREQ & 0xFF0000)>>16;
Write_Micro(2,d2);
/*write Byte 1*/
d1=(NCO_FREQ & 0xFF00)>>8;
Write_Micro(1,d1);
/*write Byte 0, Byte 0 is written last and
causes an internal write to occur*/
d0=NCO_FREQ & 0xFF;
Write_Micro(0,d0);
}
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