- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373890 > AD6623PCB (Analog Devices, Inc.) 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP PDF資料下載
參數(shù)資料
| 型號： | AD6623PCB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 4-Channel, 104 MSPS Digital Transmit Signal Processor TSP |
| 中文描述： | 4通道，104 MSPS的數(shù)字傳輸信號處理器判刑 |
| 文件頁數(shù)： | 33/40頁 |
| 文件大?。?/td> | 381K |
| 代理商： | AD6623PCB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
REV. 0
AD6623
–33–
Channel Function Registers (continued)
Internal Address
Bit
AD6622 Compatible Description
AD6623 Extensions Description
2. Update RCF Mode Select registers
marked with
“
2
”
.
3. Ramp Up (if Ramp is enabled)
No Change
No Change
Ch. A RCF FIR
–
PSK Magnitude 0
Ch. A RCF FIR
–
PSK Magnitude 1
Ch. A RCF FIR
–
PSK Magnitude 2
Ch. A RCF FIR
–
PSK Magnitude 3
Ch. A Serial Data Frame Input Select
0x: Internal Frame Request
10: External SDFI Pad
11: Previous Channel
’
s Frame End
Ch. A Serial Data Frame Output Select
0: Serial Data Frame Request
1: Serial Data Frame End
Ch. A Serial Clock Slave (SCS)
SCS = 0: Master Mode
(SCLK is an output)
SCS = 1: Slave Mode
(SCLK is an input)
Ch. A Serial Fine Scale Enable
1
Ch. A Serial Time Slot Sync Enable
(ignored in FIR mode)
Ch. A Ramp Interpolation Enable
Ch. A Ramp Enable
Ch. A Mode 0 Ramp Length, R0
–
1
Ch. A Mode 1 Ramp Length, R1
–
1
Ch. A Ramp Rest Time, Q
(No inputs requested during rest time.)
No Change
No Change
No Change
Ch. A Ramp RAM
No Change
This address is mirrored at 0x900
–
0x97F
and contiguously extended at 0x980
–
0x9FF
0x110
0x111
0x112
0x113
0x114
0x115
0x116
15
–
0
15
–
0
15
–
0
15
–
0
15
–
0
15
–
7
–
6
Ch. A RCF Phase EQ Coef1
Ch. A RCF Phase EQ Coef2
Unused
Unused
Unused
Unused
Unused
5
Unused
4
Unused
3
2
Unused
Unused
1
0
5
–
0
4
–
0
4
–
0
Unused
Unused
Unused
Unused
Unused
0x117
0x118
0x119
0x11A
–
11F
0x120
–
13F
0x140
–
17F
Unused
Ch. A Data RAM
Unused
Unused
Ch. A Coefficient RAM
15
–
0
15
–
14
13
–
0
15
–
0
0x180
–
1FF
NOTES
1
Clear on
RESET
.
2
These bits update after a Start or a Beam Sync. See CR 0x10F.
3
Allows dynamic updates.
(0x000) Summation Mode Control
Controls features in the summation block of the AD6623.
Bit 5
–
6:
Reserved.
Bit 4:
Low: Wideband Input Enabled.
High: Wideband Input Disabled.
Bit 3:
Low: Dual Output Disabled.
High: Dual Output Enabled.
Bit 2:
Reserved.
Bit 1:
Low: Output data will be in two
’
s complement.
High: Output data will be in offset binary.
Bit 0:
Low: Over-range will wrap.
High: Over-range will clip to full scale.
(0x001) Sync Mode Control
Bit 7:
Ignores all but the first pin sync.
Bit 6:
Beam on pin Sync.
Bit 5:
Hop on pin Sync.
Bit 4:
High enables the count down of the Start Hold-Off
Counter. The counter is clocked with the AD6623
CLK signal. When it reaches a count of one the Sleep
bit of the appropriate channel(s) is set low to activate
the channel(s).
High enables synchronization of these channels.
See the
Synchronization section of the data sheet for
detailed explanation.
(0x002) BIST Counter
Sets the length, in CLK cycles, of the built-in self test.
(0x003) BIST Result
A read-only register containing the result after a self test. Must be
compared to a known good result for a given setup to determine
pass/fail.
Bit 3
–
0:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD6624AS | Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AABC | Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6630AR-REEL | Differential, Low Noise IF Gain Block with Output Clamping |
| AD6630AR | Differential, Low Noise IF Gain Block with Output Clamping |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6623S/PCB | 制造商:Analog Devices 功能描述:4-CH, 104 MSPS DGTL TRANSMIT SGNL PROCESSOR (TSP) 28SOIC - Bulk |
| AD6624 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) |
| AD6624A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) |
| AD6624AABC | 制造商:Advanced Micro Devices 功能描述: |
| AD6624AABCZ | 功能描述:DIGITAL SIGNAL PROC 196 CSP-BGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。