參數(shù)資料
型號(hào)： AD602JCHIPS
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： Dual, Low Noise, Wideband Variable Gain Amplifiers
中文描述： SPECIALTY ANALOG CIRCUIT, UUC
封裝： DIE
文件頁(yè)數(shù)： 13/28頁(yè)
文件大小： 432K
代理商： AD602JCHIPS
AD600/AD602
The gains are offset such that A2’s gain is increased only after
A1’s gain has reached its maximum value (see Figure 26). Note
that for a differential input of 700 mV or less, the gain of a
single amplifier (A1 or A2) is at its minimum value of 1.07 dB;
for a differential input of +700 mV or more, the gain is at its
maximum value of +41.07 dB. Control inputs beyond these
limits do not affect the gain and can be tolerated without damage or
foldover in the response. See the Specifications section for more
details on the allowable voltage range. The gain is now
Gain
(dB) = 32
V
C
Rev. E | Page 13 of 28
(3)
where
V
C
is the applied control voltage.
+41.07dB
+20dB
+1.07dB
–0.56dB
–1.07dB
+40.56dB
+38.93dB
8
0
9
2
9
5
GAIN
(dB)
*
GAIN OFFSET OF 1.07dB, OR 33.44mV
A1
A2
*
*
2.5
80
1.875
60
1.25
40
0.625
20
0
0
–2.14
V
C
(V)
82.14
0
Figure 26. Explanation of Offset Calibration for Sequential Control
When V
C
is set to zero, V
G1
= 0.592 V and the gain of A1 is
1.07 dB (recall that the gain of each amplifier section is 0 dB for
V
G
= 625 mV); meanwhile, V
G2
= 1.908 V, so the gain of A2 is
1.07 dB. The overall gain is thus 0 dB (see Figure 23). When
V
C
= 1.25 V, V
G1
= 1.25 V – 0.592 V = 0.658 V, which sets the
gain of A1 to 40.56 dB, while V
G2
= 1.25 V – 1.908 V = 0.658 V,
which sets A2’s gain at 0.56 dB. The overall gain is now 40 dB
(see Figure 24). When V
C
= 2.5 V, the gain of A1 is 41.07 dB and
the gain of A2 is 38.93 dB, resulting in an overall gain of 80 dB
(see Figure 25). This mode of operation is further clarified by
Figure 27, which is a plot of the separate gains of A1 and A2 and
the overall gain vs. the control voltage. Figure 28 is a plot of the
gain error of the cascaded amplifiers vs. the control voltage.
PARALLEL MODE (SIMPLEST GAIN-CONTROL
INTERFACE)
In this mode, the gain-control voltage is applied to both inputs
in parallel—C1HI and C2HI are connected to the control
voltage, and C1LO and C2LO are optionally connected to an
offset voltage of 0.625 V. The gain scaling is then doubled to
64dB/V, requiring only 1.25 V for an 80 dB change of gain. In
this case, the amplitude of the gain ripple is also doubled, as is
shown in Figure 29, and the instantaneous SNR at the output of
A2 decreases linearly as the gain is increased (see Figure 30).
LOW RIPPLE MODE (MINIMUM GAIN ERROR)
As can be seen in Figure 28 and Figure 29, the output ripple is
periodic. By offsetting the gains of A1 and A2 by half the
period of the ripple, or 3 dB, the residual gain errors of the two
amplifiers can be made to cancel. Figure 31 shows the much
lower gain ripple when configured in this manner. Figure 32
plots the SNR as a function of gain; it is very similar to that in
the parallel mode.
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