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參數(shù)資料
| 型號： | AD5623RBRMZ-5REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT DUAL 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 3µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 287k |
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Data Sheet
AD5623R/AD5643R/AD5663R
Rev. E | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05858-
003
1
VOUTA
10
VREFIN/VREFOUT
2
VOUTB
9
VDD
3
GND
8
DIN
4
LDAC
7
SCLK
5
CLR
6
SYNC
AD5623R/
AD5643R/
AD5663R
TOP VIEW
(Not to Scale)
NOTE:
EXPOSED PAD TIED TO GND ON
LFCSP PACKAGE.
Figure 3. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3
GND
Ground. Reference point for all circuitry on the part.
4
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.
5
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. While CLR is low, all LDAC pulses are
ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V.
The part exits clear code mode on the 24th falling edge of the next write to the part. If CLR is activated during
a write sequence, the write is aborted.
6
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data.
When SYNC goes low, it enables the input shift register, and data is transferred in on the falling edges of the
following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge,
in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC.
7
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input.
Data can be transferred at rates up to 50 MHz.
8
DIN
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge
of the serial clock input.
9
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with
a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
10
VREFIN/VREFOUT
Common Reference Input/Reference Output. When the internal reference is selected, this is the reference output
pin. When using an external reference, this is the reference input pin. The default for this pin is a reference input.
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