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參數(shù)資料
| 型號： | AD5623RBRMZ-5REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT DUAL 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時間： | 3µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 287k |
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Data Sheet
AD5623R/AD5643R/AD5663R
Rev. E | Page 25 of 32
MICROPROCESSOR INTERFACING
AD5623R/AD5643R/AD5663R to Blackfin ADSP-BF53X
Interface
Figure 56 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the Blackfin ADSP-BF53X micro-
processor. The ADSP-BF53X processor family incorporates two
dual-channel synchronous serial ports, SPORT1 and SPORT0,
for serial and multiprocessor communications. Using SPORT0
to connect to the AD5623R/AD5643R/AD5663R, the setup for
the interface is as follows: DT0PRI drives the DIN pin of the
AD5623R/AD5643R/AD5663R, while TSCLK0 drives the
SCLK of the parts. The SYNC is driven from TFS0.
AD5643R/
AD5663R1
ADSP-BF53x1
SYNC
TFS0
DIN
DTOPRI
SCLK
TSCLK0
1ADDITIONAL PINS OMITTED FOR CLARITY.
05858-
037
Figure 56. AD5623R/AD5643R/AD5663R to Blackfin ADSP-BF53X Interface
AD5623R/AD5643R/AD5663R to 68HC11/68L11
Interface
Figure 57 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the 68HC11/68L11 microcontroller.
SCK of the 68HC11/68L11 drives the SCLK of the AD5623R/
AD5643R/AD5663R, and the MOSI output drives the serial
data line of the DAC.
AD5643R/
AD5663R1
68HC11/68L111
SYNC
PC7
SCLK
SCK
DIN
MOSI
1ADDITIONAL PINS OMITTED FOR CLARITY.
05858-
038
Figure 57. AD5623R/AD5643R/AD5663R to 68HC11/68L11 Interface
The SYNC signal is derived from a port line (PC7). The setup
conditions for correct operation of this interface are as follows:
the 68HC11/68L11 is configured with its CPOL bit as 0, and its
CPHA bit as 1. When data is being transmitted to the DAC, the
SYNC line is taken low (PC7). When the 68HC11/68L11 is
configured as described previously, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. To load data to the AD5623R/
AD5643R/AD5663R, PC7 is left low after the first eight bits are
transferred, and a second serial write operation is performed to
the DAC. PC7 is taken high at the end of this procedure.
AD5623R/AD5643R/AD5663R to 80C51/80L51 Interface
Figure 58 shows a serial interface between the AD5623R/
AD5643R/AD5663R and the 80C51/80L51 microcontroller.
The setup for the interface is as follows: TxD of the 80C51/
80L51 drives SCLK of the AD5623R/AD5643R/AD5663R,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to the
AD5623R/AD5643R/AD5663R, P3.3 is taken low. The 80C51/
80L51 transmit data in 8-bit bytes only; thus, only eight falling
clock edges occur in the transmit cycle. To load data to the
DAC, P3.3 is left low after the first eight bits are transmitted,
and a second write cycle is initiated to transmit the second byte
of data. P3.3 is taken high following the completion of this cycle.
The 80C51/80L51 output the serial data in a format that has the
LSB first. The AD5623R/AD5643R/AD5663R must receive data
with the MSB first. The 80C51/80L51 transmit routine should
take this into account.
AD5643R/
AD5663R1
80C51/80L511
SYNC
P3.3
SCLK
TxD
DIN
RxD
1ADDITIONAL PINS OMITTED FOR CLARITY.
05858-
039
Figure 58. AD5623R/AD5643R/AD5663R to 80C512/80L51 Interface
AD5623R/AD5643R/AD5663R to MICROWIRE Interface
Figure 59 shows an interface between the AD5623R/AD5643R/
AD5663R and any MICROWIRE-compatible device. Serial data is
shifted out on the falling edge of the serial clock and is clocked into
the AD5623R/AD5643R/AD5663R on the rising edge of the SK.
AD5643R/
AD5663R1
MICROWIRE1
SYNC
CS
SCLK
SK
DIN
SO
1ADDITIONAL PINS OMITTED FOR CLARITY.
05858-
040
Figure 59. AD5623R/AD5643R/AD5663R to MICROWIRE Interface
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