- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄8729 > AD5623RBRMZ-5REEL7 (Analog Devices Inc)IC DAC NANO 12BIT DUAL 10-MSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD5623RBRMZ-5REEL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/32頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT DUAL 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 3µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 287k |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)
Data Sheet
AD5623R/AD5643R/AD5663R
Rev. E | Page 21 of 32
At this stage, the SYNC line can be kept low or be brought high.
In either case, it must be brought high for a minimum of 15 ns
before the next write sequence, so that a falling edge of SYNC
can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 2 V
than it does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation. As mentioned
previously, it must, however, be brought high again just before
the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 24 bits wide (see Figure 52). The first
two bits are don’t cares. The next three are Command Bit C2 to
Command Bit C0 (see Table 8), followed by the 3-bit DAC
Address A2 to DAC Address A0 (see Table 9), and, finally, the
16-, 14-, and 12-bit data-word.
The data-word comprises the 16-, 14-, and 12-bit input codes,
followed by zero, two, or four don’t care bits, for the AD5663R,
AD5643R, and AD5623R, respectively (see Figure 51, Figure 52,
and Figure 53). The data bits are transferred to the DAC register
on the 24th falling edge of SCLK.
Table 8. Command Definition
C2
C1
C0
Command
0
Write to Input Register n
0
1
Update DAC Register n
0
1
0
Write to Input Register n, update all
(software LDAC)
0
1
Write to and update DAC Channel n
1
0
Power down DAC (power up)
1
0
1
Reset
1
0
LDAC register setup
1
Internal reference setup (on/off)
Table 9. Address Command
A2
A1
A0
ADDRESS (n)
0
DAC A
0
1
DAC B
0
1
0
Reserved
0
1
Reserved
1
All DACs
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK, and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset, and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 54).
X
C2
C1
C0
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-
034
Figure 51. AD5663R Input Shift Register Contents
X
C2
C1
C0
A2
A1
A0
X
D11
D10
D13
D12
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-
071
Figure 52. AD5643R Input Shift Register Contents
X
C2
C1
C0
A2
A1
A0
X
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DB23 (MSB)
DB0 (LSB)
COMMAND BITS
ADDRESS BITS
DATA BITS
05858-
072
Figure 53. AD5623R Input Shift Register Contents
DIN
DB23
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24TH FALLING EDGE
SYNC
SCLK
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24TH FALLING EDGE
05858-
035
Figure 54. SYNC Interrupt Facility
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5623RBRMZ-3REEL7 | IC DAC NANO 12BIT DUAL 10-MSOP |
| AD5312BRMZ-REEL7 | IC DAC 10BIT DUAL R-R 10-MSOP |
| VI-J6K-MZ-F4 | CONVERTER MOD DC/DC 40V 25W |
| VE-B2M-MX | CONVERTER MOD DC/DC 10V 75W |
| VI-J6K-MZ-F3 | CONVERTER MOD DC/DC 40V 25W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5624 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2.7 V to 5.5 V, 450 レA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs |
| AD5624BCPZ-250RL7 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2.7 V to 5.5 V, 450 レA, Rail-to-Rail Output, Quad, 12-/16-Bit nanoDACs |
| AD5624BCPZ-R2 | 功能描述:IC DAC NANO 12BIT QUAD 10-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類(lèi)型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5624BCPZ-REEL7 | 功能描述:IC DAC NANO 12BIT QUAD 10-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:* |
| AD5624BRMZ | 功能描述:IC DAC NANO 12BIT QUAD 10-MSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類(lèi)型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。