V
參數(shù)資料
型號(hào)： AD5582YRVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/20頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT QUAD VOUT 48-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 39
設(shè)置時(shí)間： 5µs
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字，雙 ±
功率耗散（最大）： 30mW
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TFSOP（0.240"，6.10mm 寬）
供應(yīng)商設(shè)備封裝： 48-TSSOP
包裝： 管件
輸出數(shù)目和類(lèi)型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 200k
產(chǎn)品目錄頁(yè)面： 783 (CN2011-ZH PDF)
REV. A
–4–
AD5582/AD5583
Parameter
Symbol
Condition
Min
Typ
1
Max
Unit
LOGIC INPUTS/OUTPUTS
Logic Input Low Voltage
VIL
0.8
V
DVDD = 3 V
± 10%
0.4
V
Logic Input High Voltage
VIH
2.4
V
DVDD = 3 V
± 10%
2.1
V
Input Leakage Current
IIL
mA
Input Capacitance
4
CIL
pF
Output Voltage High
VOH
IOH = –0.8 mA
2.4
V
Output Voltage Low
VOL
IOL = 1.2 mA, TA = 85 C,
0.4
V
IOL = 0.6 mA, DVDD = 3 V
VOL
IOL = 1.0 mA, TA = 125 C,
0.4
V
IOL = 0.5 mA, DVDD = 3 V
AC CHARACTERISTICS
Output Slew Rate
SR
Data = Zero Scale to Full Scale
2
V/
ms
to Zero Scale
Settling Time
8
tS
To
±0.1% of Full Scale
14
ms
DAC Glitch
Q
Code 7FFH to 800H to 7FFH for
100
nV-s
AD5582 and 1FFH to 200H to
1FFH for AD5583
Digital Feedthrough
VOUT/tCS
Data = Midscale,
CS Toggles at
5
nV-s
f = 16 MHz
Analog Crosstalk
VOUT/VREF
VREF = 1.5 V dc + 1 V p-p,
–80
dB
Data = 000H, f = 100 kHz
Output Noise
eN
f = 1 kHz
33
nV/
÷Hz
SUPPLY CHARACTERISTICS
Single-Supply Voltage Range
VDD
VSS = 0 V
3
16.5
V
Dual-Supply Voltage Range
VDD/VSS
VDD = +2.7 V to +6.5 V,
–6.5
+6.5
V
VSS = –6.5 V to –2.7 V
Digital Logic Supply
DVDD
2.7
6.5
V
Positive Supply Current
6
IDD
VIL = 0 V, No Load
2.3
3.5
mA
Power Dissipation
PDISS
VIL = 0 V, No Load
34.5
52.5
mW
Power Supply Sensitivity
PSS
VDD =
±5%
30
ppm/V
NOTES
1Typical specifications represent average readings measured at 25
∞C.
2DAC Output Equation: V
OUT = VREFL + [(VREFH – VREFL)
D/2
N], where D = data in decimal loaded in corresponding DAC Register A, B, C, D, and N equals the number of
bits; AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V REFH – VREFL)/4096 V and = (VREFH – VREFL)/1024 V for AD5582 and AD5583, respectively.
3The first two codes (000
H, 001H) of the AD5583 and the first four codes (000 H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.
4These parameters are guaranteed by design and not subject to production testing.
5Dual-supply operation, V
REFL = VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.
6Short circuit output and supply currents are 24 mA and 25 mA, respectively.
7Part is stable under any capacitive loading conditions.
8The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.
Specifications subject to change without notice.
ELECTRICAL CHARACTERISTICS (continued)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD5582YRVZ 制造商:Analog Devices 功能描述:QUAD 12BIT DAC SMD 5582 TSSOP48
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