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參數(shù)資料
| 型號： | AD5582YRVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD VOUT 48-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 設(shè)置時間： | 5µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 200k |
| 產(chǎn)品目錄頁面： | 783 (CN2011-ZH PDF) |
REV. A
–18–
AD5582/AD5583
In this circuit, the inverting input of the op amp forces the VO to
be equal to the DAC output. The load current is then delivered by
the supply via the N-Ch FET N1. U3 needs to be a rail-to-rail
input type. With a VDD of 5 V, this circuit can source a maximum
of 200 mA at 4.096 V full scale, 100 mA at midscale, and 50 mA
near zero-scale outputs. Higher current can be achieved with N1
in a larger package mounted on a heat sink.
Programmable PGA
The AD603 is a low noise, voltage controlled amplifier for use in
RF and IF AGC (automatic gain control) systems. It provides
accurate, pin selectable gains of –11 dB to +31 dB with a band-
width of 90 MHz, or 9 dB to 51 dB with a bandwidth of 9 MHz.
Any intermediate gain range may be arranged using one external
resistor between Pin 5 and Pin 7. The input referred noise spectral
density is only 1.3 nV/
÷Hz and power consumption is 125 mW
at the recommended
±5 V supplies.
U4
AD8565
–
+
U1
AD5582
VREFHA
VREFHB
VREFHC
VREFHD
VREFLA
VREFLB
VREFLC
VREFLD
VOA VOB VDD1-TO-3 VOC VOD
DVDD
VSS1-TO-3
–IN
U2
ADR510
+IN
–IN
U3
ADR510
+IN
DECOUPLING CAPS ARE OMITTED FOR CLARITY
R1
10k
R2
10k
VDD
1.0V
2.0V
VDD
R4
50k
R3
50k
VDD
R1
100
VIN
G–
G+
VINP
V–
V+
OUT
U5
AD603
0.1 F
C1
VDD
COMM
FDBK
G–
G+
VINP
V–
V+
OUT
U6
AD603
VDD
COMM
FDBK
+10V
VO
0.1 F
C2
0.1 F
C3
Figure 8. Programmable PGA
The decibel gain is linear in dB, accurately calibrated, and stable
over temperature and supply. The gain is controlled at a high
impedance (50 M
W), low bias (200 nA) differential input; the
scaling is 25 mV/dB, requiring a gain control voltage of only 1 V
to span the central 40 dB of the gain range. An overrange and
underrange of 1 dB is provided whatever the selected range. The
gain control response time is less than 1 ms for a 40 dB change.
The differential gain control interface allows the use of either
differential or single-ended positive or negative control voltages,
where the common-mode range is –1.2 V to +2.0 V. The
AD5582/AD5583 is ideally suited to provide the differential
input range of 1 V within the common-mode range of 0 V to 2 V.
To accomplish this, place VREFH at 2.0 V and VREFL at 1.0 V,
then all 4096 V levels of the AD5582 will fall within the gain
control range of the AD603. Please refer to the AD603 data
sheet for further information regarding gain control, layout, and
general operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5582YRVZ | 制造商:Analog Devices 功能描述:QUAD 12BIT DAC SMD 5582 TSSOP48 |
| AD5582YRVZ-REEL | 功能描述:IC DAC 12BIT PARALLEL IN 48TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD5583 | 制造商:AD 制造商全稱:Analog Devices 功能描述:QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter |
| AD5583YRU-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:QUAD, Parallel-Input, Voltage Output, 12-/10-Bit Digital-to-Analog Converter |
| AD5583YRV | 制造商:Analog Devices 功能描述:DAC 4-CH R-2R 10-bit 48-Pin TSSOP 制造商:Rochester Electronics LLC 功能描述:QUAD 10BIT DAC PARALLEL IN - Bulk |
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