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參數(shù)資料
| 型號： | AD5555CRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual, Current-Output, Serial-Input, 16-/14-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | AD5555CRU |
AD5545/AD5555
Table 5. AD5555 Control Logic Truth Table
CS
CLK
LDAC
H
X
H
L
L
H
L
↑
+
H
RS
H
H
H
MSB
X
X
X
Serial Shift Register Function
No Effect
No Effect
Shift Register Data
Advanced One Bit
No Effect
No Effect
Input Register Function
Latched
Latched
Latched
DAC Register
Latched
Latched
Latched
L
↑
+
H
L
H
H
H
H
X
X
Latched
Selected DAC Updated
with Current SR Current
Latched
Latched
Latched
Latched Data = 0x0000
Latched Data = 0x2000
Latched
Latched
H
H
H
H
H
X
X
X
X
X
L
H
↑
+
H
H
H
H
H
L
L
X
X
X
0
H
No Effect
No Effect
No Effect
No Effect
No Effect
Transparent
Latched
Latched
Latched Data = 0x0000
Latched Data = 0x2000
NOTES
1. SR = Shift Register,
↑
+ = Positive Logic Transition, and X = Don’t Care.
2. At power-on, both the input register and the DAC register are loaded with all 0s.
Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position
B17
B16
B15
B14
B13
Data Word
A1
A0
D15
D14
D13
B12
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only
the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format
MSB
Bit Position
B15
B14
B13
B12
Data Word
A1
A0
D13
D12
B11
D11
B10
D10
B9
D9
B8
D8
B7
D7
B6
D6
B5
D5
B4
D4
B3
D3
B2
D2
B1
D1
LSB
B0
D0
Note that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge
returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the
decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only
the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied logic low to disable the DAC registers.
Table 8. Address Decode
A1
A0
DAC Decoded
0
0
None
0
1
DAC A
1
0
DAC B
1
1
DAC A and DAC B
Rev. 0 | Page 8 of 16
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