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| 型號(hào)： | AD5555CRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual, Current-Output, Serial-Input, 16-/14-Bit DAC |
| 中文描述： | SERIAL INPUT LOADING, 0.5 us SETTLING TIME, 14-BIT DAC, PDSO16 |
| 封裝： | MO-153AB, TSSOP-16 |
| 文件頁(yè)數(shù)： | 13/16頁(yè) |
| 文件大?。?/td> | 1419K |
| 代理商： | AD5555CRU |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)當(dāng)前第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
AD5545/AD5555
APPLICATIONS
STABILITY
Rev. 0 | Page 13 of 16
AD5545/AD5555
AD8628
V
REF
V
REF
I
OUT
V
O
V
DD
V
DD
R
FB
U1
U2
C1
GND
02918-0-020
Figure 20. Operational Compensation Capacitor for Gain Peaking Prevention
In the I-to-V configuration, the I
OUT
of the DAC and the invert-
ing node of the op amp must be connected as close as possible,
and proper PCB layout techniques must be employed. Since
every code change corresponds to a step function, gain peaking
may occur if the op amp has limited GBP, and if there is exces-
sive parasitic capacitance at the inverting node.
An optional compensation capacitor, C1, can be added for sta-
bility as shown in Figure 20. C1 should be found empirically, but
20 pF is generally more than adequate for the compensation.
POSITIVE VOLTAGE OUTPUT
To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the resis-
tors’ tolerance errors. To generate a negative reference, the
reference can be level shifted by an op amp such that the V
OUT
and GND pins of the reference become the virtual ground and
–2.5 V, respectively (see Figure 21).
AD5545/AD5555
1/2
AD8628
1/2
AD8620
V–
ADR03
V
REF
I
OUT
V
OUT
V
IN
V
DD
GND
GND
02918-0-021
V
O
0 < V
O
< +2.5
R
FB
U2
U1
+5V
V+
–5V
+5V
–2.5V
U3
C1
U4
Figure 21. Positive Voltage Output Configuration
BIPOLAR OUTPUT
The AD5545/AD5555 is inherently a 2-quadrant multiplying
D/A converter. It can easily set up for unipolar output opera-
tion. The full-scale output polarity is the inverse of the reference
input voltage.
In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier,
U4, configured as a summing amplifier (see Figure 22). In this
circuit, the second amplifier, U4, provides a gain of +2, which
increases the output span magnitude to 5 V. Biasing the external
amplifier with a 2.5 V offset from the reference voltage results in a
full 4-quadrant multiplying circuit. The transfer equation of this
circuit shows that both negative and positive output voltages are
created because the input data (
D
) is incremented from code zero
(
V
OUT
= –2.5 V) to midscale (
V
OUT
= 0 V) to full scale (
V
OUT
=
+2.5 V).
(
)
(
5545
1
–
768
,
32
/
AD
V
D
V
REF
OUT
×
)
=
(3)
(
)
(
5555
1
–
384
,
16
/
AD
V
D
V
REF
OUT
×
)
=
(4)
For the AD5545, the external resistance tolerance becomes the
dominant error that users should be aware of.
AD5545/AD5555
1/2
AD8620
1/2
AD8620
V–
ADR03
V
REF
I
OUT
V
OUT
V
IN
V
DD
GND
GND
02918-0-022
V
O
–2.5 < V
O
< +2.5
R
FB
U2
U3
U1
+5V
+5V
V+
–5V
5V
U4
C1
C2
R1
10k
±
0.01%
10k
±
0.01%
5k
±
0.01%
R2
R3
Figure 22. Four-Quadrant Multiplying Application Circuit
PROGRAMMABLE CURRENT SOURCE
Figure 23 shows a versatile V-to-I conversion circuit using
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec-
tional current flow and high voltage compliance. This circuit
can be used in a 4 mA to 20 mA current transmitter with up to
a 500 of load. In Figure 23, it shows that if the resistor net-
work is matched, the load current is
(
)
D
V
3
1
3
2
REF
×
×
+
R
=
R
R
R
I
L
(5)
R
3, in theory, can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that the AD8510 can deliver ±20 mA in both
directions, and the voltage compliance approaches 15 V, which
is mainly limited by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes
(
)
′
)
2
(
(
)
3
R
1
–
3
2
1
2
R
1
3
1
R
R
R
R
R
′
R
R
R
+
′
Z
O
+
+
′
=
(6)
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