參數(shù)資料
型號: AD5541
廠商: Analog Devices, Inc.
英文描述: 5V Supply,Serial Input,Voltage Output,16-Bit DACs(16位的5V電源、串行輸入、電壓輸出的D/A轉(zhuǎn)換器)
中文描述: 5V電源,電壓輸出,16串行輸入位DAC(16位的5V的電源,串行輸入,電壓輸出的的D / A轉(zhuǎn)換器)
文件頁數(shù): 8/9頁
文件大?。?/td> 130K
代理商: AD5541
AD5541/AD5542
–8–
REV. PrD
Prelimnary Technical Data
PRELMNARY
DATA
+V
REF
* (32,767/32,768)
+V
REF
* (1/32,768)
0V
TECHNCAL
from the serial register. However, the serial register is not
cleared on power up, so its contents are undefined. When
loading data initially to the DAC, 16 bits or more should
be loaded to prevent erroneous data appearing on the out-
put. If more than 16 bits are loaded, then the last 16 are
kept, and if less than 16 are loaded, then bits will remain
from the previous word. If the AD5541/5542 needs to be
interfaced with data shorter than 16 bits, then the data
should be padded with zeros at the LSBs.
OUT PUT A MPL IF IE R SE L E C T ION
For bipolar mode, a precision amplifier should be used,
supplied from a dual power supply, this will provide the
±V
REF
output. In a single supply application, selection of a
suitable opamp may be more difficult as the output swing
of the amplifier does not usually include the negative rail,
in this case AGND. T his can result in some degradation
of the specified performance unless the application does
not use codes near zero.
T he selected opamp needs to have very low offset voltage,
(the DAC LSB is 38
μ
V with a 2.5 V reference), to elimi-
nate the need for output offset trims. Input bias current
should also be very low as the bias current multiplied by
the DAC output impedance (approx. 6k) will add to the
zero code error. Rail to rail input and output performance
is required. For fast settling, the slew rate of the opamp
should not impede the settling time of the DAC. Output
impedance of the DAC is constant and code independent,
T able 2. Bipolar Code T able
DAC Latch Contents
MSB
Analog Output
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
-V
REF
* (1/32,768)
-V
REF
* (32,768/32,768) = -V
REF
0000 0000 0000 0000
BIPOL A R OUT PUT OPE R A T ION
With the aid of an external opamp, the AD5542 may be
configured to provide a bipolar voltage output. A typical
circuit of such operation is shown in Figure 4. T he
matched bipolar offset resistors R
FB
and R
INV
are connected
to an external opamp to achieve this bipolar output swing.
T able 2 shows the transfer function for this output operat-
ing mode. Also provided on the AD5542 are a set of K el-
vin connections to the analog ground inputs.
Figure 4. Bipolar Output (AD5542 only).
but in order to minimise gain errors, the input impedance
of the output amplifier should be as high as possible. T he
amplifier should also have a 3dB bandwidth of 1MHz or
greater. T he amplifier adds another time constant to the
system, hence increasing the settling time of the output. A
higher 3dB amplifier bandwidth, results in a shorter effec-
tive settling time of the combined DAC and amplifier.
F OR C E SE NSE A MPL IF IE R SE L E C T ION
T hese amplifiers will be single supply, low noise amplifi-
ers. A low output impedance at high frequencies is pre-
ferred as they need to be able to handle dynamic currents
of up to ±20mA.
As the input impedance is code dependant, the reference
pin should be driven from a low impedance source. T he
AD5541/5542 operates with a voltage reference ranging
from +2 V to V
DD
. T he DAC’s full scale output voltage is
determined by the reference. T ables 1 and 2 outline the
analog output voltage for particular digital codes. For
optimum performance, K elvin sense connections are pro-
vided on the AD5542.
If the application doesn’t require separate force and sense
lines, they should be tied together close to the package to
internal die.
POWE R ON RE SE T
T hese parts have a power on reset function to ensure the
output is at a known state upon power up. On power up,
the DAC register contains all zeros, until data is loaded
POWE R SUPPL Y A ND R E F E R E NC E BY PA SSING
For accurate high resolution performance, it is recom-
mended that the reference and supply pins be bypassed
with a 10
μ
F tantalum capacitor in parallel with a 0.1
μ
F
ceramic capacitor.
AD5542
DGND
VDD
CS
REFS
REFF
OUT
SCLK
DIN
AGNDS
0.1
μ
F
0.1
+5V
+2.5V
EXTERNAL OP AMP
BIPOLAR
OUTPUT
LDAC
10
μ
F
μ
F
SERIAL
INTERFACE
AGNDF
RINV
RFB
RFB
INV
+5V
-5V
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