參數(shù)資料
型號: AD5541
廠商: Analog Devices, Inc.
英文描述: 5V Supply,Serial Input,Voltage Output,16-Bit DACs(16位的5V電源、串行輸入、電壓輸出的D/A轉(zhuǎn)換器)
中文描述: 5V電源,電壓輸出,16串行輸入位DAC(16位的5V的電源,串行輸入,電壓輸出的的D / A轉(zhuǎn)換器)
文件頁數(shù): 3/9頁
文件大?。?/td> 130K
代理商: AD5541
AD5541/AD5542
–3–
REV. PrD
Prelimnary Technical Data
PRELMNARY
DATA
t9
TECHNCAL
Figure 1. Timing Diagram
TIMNGCHARACTERISTICS
1,2
Parameter
Limit at T
MIN
, T
MAX
All Versions
Units
Description
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
25
40
20
20
15
15
35
20
15
0
30
30
30
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCL K cycle frequency
SCL K cycle time
SCL K high time
SCL K low time
CS
low to SCLK high setup
CS
high to SCLK high setup
SCLK high to
CS
low hold time
SCLK high to
CS
high hold time
Data Hold time
LDAC
pulse width
CS
high to
LDAC
low setup
CS
high time between active periods
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90%
of V
DD
) and timed from a voltage level of (V
IL
+V
IH
)/2.
Specifications subject to change without notice.
SCLK
t2
t
t1
CS
DIN
DB15
3
t7
LDAC*
t4
t8
DB0
t5
t6
t10
t11
*AD5542
Only. May be tied permanently low if required.
t12
(V
DD
= +5V ± 5%, V
REF
= +2.5V, AGND = DGND = 0 V. All specifications T
A
= T
MN
to T
MAX,
unless
otherwse noted.)
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