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參數(shù)資料
| 型號： | AD5541 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5V Supply,Serial Input，Voltage Output,16-Bit DACs(16位的5V電源、串行輸入、電壓輸出的D/A轉(zhuǎn)換器) |
| 中文描述： | 5V電源，電壓輸出,16串行輸入位DAC（16位的5V的電源，串行輸入，電壓輸出的的D / A轉(zhuǎn)換器） |
| 文件頁數(shù)： | 7/9頁 |
| 文件大小： | 130K |
| 代理商： | AD5541 |
AD5541/AD5542
–7–
REV. PrD
Prelimnary Technical Data
In this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependant. T he output volt-
age is dependant on the reference voltage as shown in the
following equation.
V
OUT
= V
REF
x D
2
N
where
D
is the decimal data word loaded to the DAC reg-
ister and
N
is the resolution of the DAC. For a reference
of +2.5 V, the equation simplifies to the following.
V
OUT
= 2.5 x D
65,536
giving a V
OUT
of 1.25 V with midscale loaded, and 2.5 V
with full scale loaded to the DAC.
T he LSB size is V
REF
/65,536.
TECHNCAL
Figure 2. Dac Architecture.
G E NE R A L D E SC R IP T ION
T he AD5541/5542 are single 16 bit, serial input, voltage
output DAC’s. T hey operate from a single supply ranging
from +2.7 V to +5 V and consume typically 300
μ
A with a
supply of +5 V. Data is written to these devices in a 16 bit
word format, via a three or four wire serial interface. T o
ensure a known power up state, these parts were designed
with a power on reset function. In unipolar mode the out-
put is reset to 0V, while in bipolar mode, the AD5542
output is set to -V
REF
. K elvin sense connections for the
reference and analog ground are included on the AD5542.
D igital-to-A nalog Section
T he DAC architecture consists of two matched DAC sec-
tions. A simplified circuit diagram is shown in Figure 2.
T he DAC architecture of the AD5541/5542 is segmented.
T he 4 MSBs of the 16 bit data word are decoded to drive
15 switches E1 to E15. Each of these switches connects
one of 15 matched resistors to either AGND or V
REF
. T he
remaining 12 bits of the data word drive switches S0 to
S11 of a 12 bit voltage mode R-2R ladder network.
T able 1. Unipolar Code T able
DAC Latch Contents
MSB
Analog Output
LSB
1111 1111 1111 1111
V
REF
* (65,535/65,536)
V
REF
* (32,768/65,536) = 1/2V
REF
V
REF
* (1/65,536)
0 V
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
AD5541/AD5542
AD820/
OP196
DGND
* AD5542 ONLY
VDD
REFS*
REF(REFF*)
OUT
SCLK
DIN
CS
AGND_
0.1
μ
F
0.1
+5V
+2.5V
EXTERNAL OP AMP
UNIPOLAR
OUTPUT
LDAC*
10
μ
F
μ
F
SERIAL
INTERFACE
Figure 3. Unipolar Output.
UNIPOL A R OUT PUT OPE R A T ION
T hese DACs are capable of driving unbuffered loads of
60k
. Unbuffered operation results in low supply current,
typically 300
μ
A, and a low offset error. T he AD5541 pro-
vides a unipolar output swing ranging from 0 V to V
REF
.
T he AD5442 can be configured to output both unipolar
and bipolar voltages. Figure 3 shows a typical unipolar
output voltage circuit. T he code table for this mode of
operation is shown in T able 1.
SE R IA L INT E R F A C E
T he AD5541 and AD5542 are controlled by a versatile
3-wire serial interface, which operates at clock rates up to
25 MHz and is compatible with SPI, QSPI,
MICROWIRE and DSP interface standards. T he timing
diagram can be seen in Figure 1. Input data is framed by
the chip select input,
CS
. After a high to low transition on
CS
, data is shifted synchronously and latched into the
input register on the rising edge of the serial clock,
SCLK . Data is loaded MSB first in 16 bit words. After 16
data bits have been loaded into the serial input register, a
low to high transition on
CS
transfers the contents of the
shift register to the DAC. Data can only be loaded to the
part while
CS
is low.
T he AD5542 has an
LDAC
function which allows the
DAC latch to be updated asynchronously by bringing
LDAC
low after
CS
goes high.
LDAC
should be main-
tained high while data is written to the shift register. Al-
ternatively,
LDAC
may be tied permanently low to update
the DAC synchronously. With
LDAC
tied permanently
low, the rising edge of
CS
will load the data to the DAC.
2R
2R
R
2R
R
2R
2R
2R
S0
S11
E1
E2
E15
2R
S1
VOUT
VREF
4 MSB's decoded into 15
equal segments
12 bit R-2R Ladder
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| AD5543BR | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
| AD5543BRM | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:D38999 Series III; No. of Contacts:4; Connector Shell Size:13; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Body Style:Straight RoHS Compliant: No |
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| AD5553CRM | Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:13-4 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD5541_12 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-Bit DACs |
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