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參數(shù)資料
| 型號(hào)： | AD5533 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85% |
| 中文描述： | 32通道無限采樣保持 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | AD5533 |
AD5533
–12–
REV. 0
Reset Function
The reset function on the AD5533 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple-
mented by applying a low-going pulse of between 50 ns and 150 ns
to the
TRACK
/
RESET
pin on the device. If the applied pulse
is less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin adopts
its track function on the selected channel, V
IN
is switched to the
output buffer and an acquisition on the channel will not occur
until a rising edge of
TRACK
.
TRACK
Function
Normally in SHA mode of operation,
TRACK
is held high and
the channel begins to acquire when it is addressed. However, if
TRACK
is low when the channel is addressed, V
IN
is switched
to the output buffer and an acquisition on the channel will not
occur until a rising edge of
TRACK
. At this stage the
BUSY
pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
V
IN
is free to change again without affecting this output value.
This is useful in an application where the user wants to ramp up
V
IN
until V
OUT
reaches a particular level (Figure 12). V
IN
does
not need to be acquired continuously while it is ramping up.
TRACK
can be kept low and only when V
OUT
has reached its
desired voltage is
TRACK
brought high. At this stage, the
acquisition of V
IN
begins.
In the example shown, a desired voltage is required on the out-
put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on V
IN
through a DAC.
TRACK
is kept low
while the voltage on V
IN
ramps up so that V
IN
is not continu-
ally acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The
μ
C/
μ
P then
knows what code is required to be input in order to obtain the
desired voltage at the DUT. The
TRACK
input is now brought
high and the part begins to acquire V
IN
.
BUSY
goes low until V
IN
has been acquired. When
BUSY
goes high, the output buffer
is switched from V
IN
to the output of the DAC.
MODES OF OPERATION
The AD5533 can be used in three different modes. These modes
are set by two mode bits, the first two bits in the serial word.
The 01 option (DAC Mode) is not available for the AD5533.
To avail of this mode refer to the AD5532 data sheet. If you
attempt to set up DAC mode, the AD5533 will enter a test-mode
and a 24-clock write will be necessary to clear this.
Table II. Modes of Operation
Mode Bit 1
Mode Bit 2
Operating Mode
0
0
1
1
0
1
0
1
SHA Mode
DAC Mode (Not Available)
Acquire and Readback
Readback
1. SHA Mode
In this standard mode a channel is addressed and that channel
acquires the voltage on V
IN
. This mode requires a 10-bit write
to address the relevant channel (V
OUT
0–V
OUT
31, offset channel
or all channels). MSB is written first.
2. Acquire and Readback Mode
This mode allows the user to acquire V
IN
and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V
IN
is acquired in 16
μ
s (max).
Following the acquisition, after the next falling edge of
SYNC
the data in the relevant DAC register is clocked out onto the
D
OUT
line in a 14-bit serial format. During readback D
IN
is
ignored. The full acquisition time must elapse before the DAC
register data can be clocked out.
3. Readback Mode
Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of
SYNC
, the data in the relevant DAC
register is clocked out onto the D
OUT
line in a 14-bit serial format.
The user must allow 400 ns (min) between the last SCLK fall-
ing edge in the 10-bit write and the falling edge of
SYNC
in
the 14-bit readback. The serial write and read words can be seen in
Figure 13.
This feature allows the user to read back the DAC register code
of any of the channels. Readback is useful if the system has been
calibrated and the user wants to know what code in the DAC
corresponds to a desired voltage on V
OUT
.
INTERFACES
SERIAL INTERFACE
The SER/
PAR
pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:
SYNC
, D
IN
, SCLK
Standard 3-wire interface pins. The
SYNC
pin is shared
with the
CS
function of the parallel interface.
D
OUT
Data Out pin for reading back the contents of the DAC regis-
ters. The data is clocked out on the rising edge of SCLK and
is valid on the falling edge of SCLK.
When this is high all 32 channels acquire V
IN
simultaneously.
The acquisition time is then 45
μ
s (typ) and accuracy may be
reduced.
Offset_Sel Bit
If this bit is set high, the offset channel is selected and Bits
A4–A0 are ignored.
Test Bit
This must be set low for correct operation of the part.
A4–A0
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5533ABC-1 | 32-Channel, 14-Bit Voltage-Output DAC |
| AD5541LR | 5 V, Serial-Input Voltage-Output, 16-Bit DACs |
| AD5542AR | 5 V, Serial-Input Voltage-Output, 16-Bit DACs |
| AD5542JR | 5 V, Serial-Input Voltage-Output, 16-Bit DACs |
| AD5541BR | 5 V, Serial-Input Voltage-Output, 16-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5533ABC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
| AD5533ABC-1REEL | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA T/R |
| AD5533ABCZ-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA |
| AD5533B | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Precision Infinite Sample-and-Hold |
| AD5533BBC-1 | 制造商:Analog Devices 功能描述:Sample and Hold 32-CH 16us 74-Pin CSP-BGA 制造商:Rochester Electronics LLC 功能描述:32 CHANNEL, INFINITE SHA ONLY I.C. - Bulk |
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