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參數(shù)資料
| 型號： | AD5530BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT SRL IN/VOUT 16TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 60mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 50k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5530/AD5531
Rev. B | Page 13 of 20
THEORY OF OPERATION
00
93
8-
02
0
SDO
LDAC
12-/14-BIT DAC
DAC REGISTER
SYNC REGISTER
16-BIT SHIFT
REGISTER
SYNC
SDIN
REFIN
14
OUTPUT
DAC ARCHITECTURE
The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode
DAC, and the AD5531 consists of a 14-bit R-2R section. Using a
5 V reference connected to the REFIN pin and REFAGND tied
to 0 V, a bipolar ±10 V voltage output results. The DAC coding
is straight binary.
SERIAL INTERFACE
Serial data on the SDIN input is loaded to the input register
under the control of SCLK, SYNC
LDAC
, and
. A write
operation transfers a 16-bit word to the AD5530/AD5531.
Figure 20. Simplified Serial Interface
Figure 19 show the contents of the input shift register. Twelve or
14 bits of the serial word are data bits; the rest are don’t cares.
Data written to the part via SDIN is available on the SDO pin 16
clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.
DB15 (MSB)
XX
D9
D10
D11
D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
DB0 (LSB)
DATA BITS
00
93
8
-01
8
PD FUNCTION
Figure 18. AD5530 Input Shift Register Contents
PD
The
pin allows the user to place the device into power-down
mode. While in this mode, power consumption is at a minimum;
the device draws only 50 μA of current. The
XX
D11
D12
D13
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DB15 (MSB)
DB0 (LSB)
00
93
8-
01
9
DATA BITS
PD function does
not affect the contents of the DAC register.
Figure 19. AD5531 Input Shift Register Contents
READBACK FUNCTION
SYNC
The serial word is framed by the signal,
. After a high-to-
low transition on
The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
SYNC, data is latched into the input shift
register on the falling edges of SCLK. There are two ways the
DAC register and output can be updated. The LDAC signal is
examined on the falling edge of SYNC; depending on its status,
either a synchronous or asynchronous update is selected. If
LDAC is low, then the DAC register and output are updated on
the low-to-high transition of SYNC. Alternatively, if LDAC is
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of SYNC. The contents of the DAC
register and the output voltage are updated by bringing LDAC
low any time after the 16-bit data transfer is complete. LDAC
can be tied permanently low if required. A simplified diagram
of the input loading circuitry is illustrated in Figure 20.
RBEN
and SDO (serial data out). When
is taken low, on
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register. RBEN can be used to frame
the readback data by leaving it low for 16 clock cycles, or it can
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word are 0s.
CLR FUNCTION
The falling edge of CLR causes VOUT to be reset to the same
potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with LDAC
after CLR is asserted high. Alternatively, if LDAC is tied low, the
output is loaded with the contents of the DAC register auto-
matically after CLR is brought high.
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參數(shù)描述 |
|---|---|
| AD5530BRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters |
| AD5530BRUZ-REEL | 功能描述:IC DAC 12BIT SERIAL IN 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5530BRUZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters |
| AD5530BRUZ-REEL7 | 功能描述:IC DAC 12BIT SERIAL IN 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5530BRUZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Serial Input, Voltage Output 12-/14-Bit Digital-to-Analog Converters |
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