DVCC, Limit at TMIN, T
參數(shù)資料
型號： AD5522JSVUZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/64頁
文件大?。?/td> 0K
描述： IC PMU QUAD 16BIT DAC 80-TQFP
產(chǎn)品變化通告： Improve FI ac crosstalk
設(shè)計資源： Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
標準包裝： 1
類型： 每引腳參數(shù)測量單元（PPMU）
應(yīng)用： 自動測試設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 80-TQFP-EP（12x12）
包裝： 托盤
AD5522
Data Sheet
Rev. E | Page 12 of 64
Parameter 1, 2, 3
DVCC, Limit at TMIN, TMAX
Unit
Description
2.3V to 2.7V
2.7V to 3.6V
4.5V to 5.25V
t16
1.8
1.2
0.9
s min
RESET pulse width low
t17
670
700
750
s max
RESET time indicated by BUSY low
t18
400
ns min
Minimum SYNC high time in readback mode
60
45
25
ns max
SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
4
Writes to more than one X1 register engages the calibration engine for longer times, shown by the BUSY low time, t10. Subsequent writes to one or more X1 registers
should either be timed or should wait until BUSY returns high (see Figure 56). This is required to ensure that data is not lost or overwritten.
5
t19 is measured with the load circuit shown in Figure 4.
6
SDO output slows with lower DVCC supply and may require use of a slower SCLK.
Table 3. LVDS Interface
DVCC, Limit at TMIN, TMAX
Parameter1, 2, 3
2.7 V to 3.6 V
4.5 V to 5.25 V
Unit
Description
t1
20
12
ns min
SCLK cycle time
t2
8
5
ns min
SCLK pulse width high and low time
t3
3
ns min
SYNC to SCLK setup time
t4
3
ns min
Data setup time
t5
5
3
ns min
Data hold time
t6
3
ns min
SCLK to SYNC hold time
45
25
ns min
SCLK rising edge to SDO valid
t8
150
ns min
Minimum SYNC high time in write mode after
X1 register write
70
ns min
Minimum SYNC high time in write mode after
any other register write
400
ns min
Minimum SYNC high time in readback mode
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
4
SDO output slows with lower DVCC supply and may require use of slower SCLK.
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