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| 型號： | AD5432YRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT MULTIPLYING 10-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | Unipolar, Precision DC Digital-to-Analog Conversion Using AD5426/32/43 8-Bit to12-Bit DACs (CN0034) Precision, Bipolar Configuration for the AD5426/32/43 8-Bit to12-Bit DACs (CN0036) AC Signal Processing Using AD5426/32/43 Current Output DACs (CN0037) Programmable Gain Element Using AD5426/32/43 Current Output DACs (CN0038) |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2.5M |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
AD5426/AD5432/AD5443
Data Sheet
Rev. G | Page 20 of 24
SERIAL INTERFACE
face that is compatible with SPI/QSPI/MICROWIRE and DSP
interface standards. Data is written to the device in 16 bit words.
This 16-bit word consists of 4 control bits and either 8 , 10 , or 12
data bits as shown in Figure 48, Figure 49, and Figure 50. The
AD5443 uses all 12 bits of DAC data. The AD5432 uses 10 bits
and ignores the 2 LSBs, while the AD5426 uses 8 bits and ignores
the last 4 bits.
Low Power Serial Interface
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC. The SYNC of
the microprocessor control. Unfinished data frames are latched
into the part and will affect the output.
DAC Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of
the DAC, as seen in Table 10. Default settings of the DAC on
power-on are as follows: Data is clocked into the shift register
on falling clock edges and daisy-chain mode is enabled.
Device powers on with zero-scale load to the DAC register
and IOUT lines.
The DAC control bits allow the user to adjust certain features
on power-on, for example, daisy-chaining may be disabled if
not in use, active clock edge may be changed to rising edge, and
DAC output may be cleared to either zero scale or midscale.
The user may also initiate a readback of the DAC register
contents for verification purposes.
Table 10. DAC Control Bits
C3
C2
C1
C0
Function Implemented
0
No operation (power-on default)
0
1
Load and update
0
1
0
Initiate readback
0
1
Reserved
0
1
0
Reserved
0
1
0
1
Reserved
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
Daisy-chain disable
1
0
1
0
Clock data to shift register on rising edge
1
0
1
Clear DAC output to zero scale
1
0
Clear DAC output to midscale
1
0
1
Reserved
1
0
Reserved
1
Reserved
DB0 (LSB)
DB15 (MSB)
C3
C2
C1
C0
X
DB7 DB6 DB5 DB4 DB3 DB2
DB0
DB1
X
DATA BITS
CONTROL BITS
03162-049
Figure 48. AD5426 8-Bit Input Shift Register Contents
DB5 DB4 DB3 DB2
DB0
DB1
DB0 (LSB)
DB15 (MSB)
C3
C2
C1
C0
DB7 DB6
DB8
DB9
X
DATA BITS
CONTROL BITS
03162-050
Figure 49. AD5432 10-Bit Input Shift Register Contents
DB7 DB6 DB5 DB4 DB3 DB2
DB0
DB0 (LSB)
DB15 (MSB)
DB1
C3
C2
C1
C0
DB11 DB10
DB8
DB9
DATA BITS
CONTROL BITS
03162-051
Figure 50. AD5443 12-Bit Input Shift Register Contents
SYNC Function
SYNC is an edge-triggered input that acts as a frame synchro-
nization signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low observing the minimum SYNC
falling to SCLK falling edge setup time, t4.
Daisy-Chain Mode
Daisy-chain is the default power-on mode. Note that the SDO
line operates with a VDD of 3.0 V to 5.5 V. To disable the daisy
chain function, write 1001 to the control word. In daisy-chain
mode, the internal gating on SCLK is disabled. The SCLK is
continuously applied to the input shift register when SYNC is
low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default, use
the control word to change the active edge) and is valid for the
next device on the falling edge (default). By connecting this line
to the DIN input on the next device in the chain, a multidevice
interface is constructed. Sixteen clock pulses are required for
each device in the system. Therefore, the total number of clock
cycles must equal 16 N where N is the total number of devices
in the chain. See the timing diagram in Figure 4.
When the serial transfer to all devices is complete, SYNC
should be taken high. This prevents any further data being
clocked into the input shift register. A burst clock containing
the exact number of clock cycles may be used and SYNC taken
high some time later. After the rising edge of SYNC, data is
automatically transferred from each device’s input shift register
to the addressed DAC.
When control bits = 0000, the device is in no operation mode.
This may be useful in daisy-chain applications where the user
does not want to change the settings of a particular DAC in the
chain. Simply write 0000 to the control bits for that DAC and
the following data bits will be ignored. To re-enable the daisy-
chain mode, if disabled, a power recycle is required.
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