參數(shù)資料
型號(hào): AD5420AREZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/32頁(yè)
文件大?。?/td> 0K
描述: IC DAC 16BIT 1CH SER 24TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
Weigh Scale Introduction
設(shè)計(jì)資源: Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
標(biāo)準(zhǔn)包裝: 62
設(shè)置時(shí)間: 10µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 1 電流,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 782 (CN2011-ZH PDF)
Data Sheet
AD5410/AD5420
Rev. F | Page 13 of 32
–0.8
–1.0
–0.6
–0.4
0
0.8
–0.2
0.4
0.6
0.2
1.0
10
15
20
25
30
35
40
07027-
015
DNL
E
RRO
R
(
L
S
B)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
Figure 19. Differential Nonlinearity Error vs. AVDD, Internal RSET
–0.010
–0.015
–0.005
0
0.010
0.005
0.020
0.015
0.025
10
15
20
25
30
35
40
07027-
016
T
O
T
AL
UNADJUS
T
E
D
E
RRO
R
(
%
F
S
R)
AVDD (V)
TA = 25°C
0mA TO 24mA RANGE
Figure 20. Total Unadjusted Error vs. AVDD, External RSET
–0.15
–0.13
–0.11
–0.09
–0.07
–0.05
–0.03
–0.01
0.01
0.03
0.05
10
15
20
25
30
35
40
T
O
T
AL
UNADJUS
T
E
D
E
RRO
R
(%
F
S
R
)
AVDD (V)
07027-
032
TA = 25°C
0mA TO 24mA RANGE
Figure 21. Total Unadjusted Error vs. AVDD, Internal RSET
0
0.5
1.0
1.5
2.0
2.5
–40
–20
0
20
40
60
80
H
E
A
D
R
OOM
V
OLTA
GE
(V)
TEMPERATURE (°C)
AVDD = 15V
IOUT = 24mA
RLOAD = 500
07027-
019
Figure 22. Compliance Voltage Headroom vs. Temperature
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
100
200
300
400
500
600
OU
T
PU
T
C
URR
E
N
T
(
A
)
TIME (s)
AVDD = 24V
TA = 25°C
RLOAD = 250
07027-
020
Figure 23. Output Current vs. Time on Power-Up
–50
–40
–30
–20
–10
0
10
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
O
UT
P
UT
CURRE
NT
(
A)
TIME (s)
AVDD = 24V
TA = 25°C
RLOAD = 250
07027-
021
Figure 24. Output Current vs. Time on Output Enable
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