- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8981 > AD5420AREZ (Analog Devices Inc)IC DAC 16BIT 1CH SER 24TSSOP PDF資料下載
參數(shù)資料
| 型號： | AD5420AREZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/32頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT 1CH SER 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures Weigh Scale Introduction |
| 設(shè)計資源： | Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098) |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm）裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP 裸露焊盤 |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD5410/AD5420
Data Sheet
Rev. F | Page 18 of 32
chain. When the serial transfer to all devices is complete,
LATCH is taken high. This latches the input data in each device
in the daisy chain. The serial clock can be a continuous or a
gated clock.
A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.
CONTROLLER
DATA IN
LATCH
SDIN
SCLK
DATA OUT
SERIAL CLOCK
CONTROL OUT
SDO
LATCH
SCLK
SDO
LATCH
SCLK
SDO
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5410/
AD5420*
AD5410/
AD5420*
AD5410/
AD5420*
07027-
035
Readback Operation
Readback mode is invoked by setting the address byte and read
should be a NOP command, which clocks out the data from the
previously addressed register, as shown in Figure 3. By default,
the SDO pin is disabled. After having addressed the AD5410/
AD5420 for a read operation, a rising edge on LATCH enables
the SDO pin in anticipation of data being clocked out. After the
data has been clocked out on SDO, a rising edge on LATCH
disables (tristate) the SDO pin once again. To read back the
data register, for example, the following sequence should be
implemented:
register. This configures the part for read mode with the
data register selected.
2. Follow this with a second write, a NOP condition, 0x000000.
During this write, the data from the data register is clocked
out on the SDO line.
Table 8. Read Address Decoding
Read Address
Function
00
Read status register
01
Read data register
10
Read control register
Table 9. Input Shift Register Contents for a Read Operation
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB2
DB1
DB0
0
1
0
Read address
1
X = don’t care.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B0V-MY-F4 | CONVERTER MOD DC/DC 5.8V 50W |
| VE-26N-MW-F1 | CONVERTER MOD DC/DC 18.5V 100W |
| AD5453YRMZ-REEL7 | IC DAC 14BIT MULTIPLYING 8-MSOP |
| VI-B0V-MY-F3 | CONVERTER MOD DC/DC 5.8V 50W |
| VE-26L-MW-F4 | CONVERTER MOD DC/DC 28V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5420AREZ-REEL7 | 功能描述:IC DAC 16BIT 1CH SER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5420BCPZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single Channel, 16-Bit, Serial Input, Current Source DAC |
| AD5420BREZ | 制造商:Analog Devices 功能描述: |
| AD5421 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power HART Modem |
| AD5421_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, Serial Input, Loop-Powered, 4 mA to 20 mA DAC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。