t1 t
參數(shù)資料
型號: AD5420AREZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 30/32頁
文件大?。?/td> 0K
描述: IC DAC 16BIT 1CH SER 24TSSOP
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計資源: Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
標準包裝: 1,000
設(shè)置時間: 10µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 950mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電流,單極
采樣率(每秒): *
Data Sheet
AD5410/AD5420
Rev. F | Page 7 of 32
DB23
SCLK
LATCH
SDIN
24
2
1
DB0
t1
t2
t6
t7
t8
t9
t10
t3
t4
t5
CLEAR
IOUT
07
02
7-
00
2
Figure 2. Write Mode Timing Diagram
SCLK
LATCH
SDIN
24
2
1
DB0
DB23
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
SDO
DB23
SELECTED REGISTER
DATA CLOCKED OUT
NOP CONDITION
UNDEFINED DATA
INPUT WORD SPECIFIES
REGISTER TO BE READ
1
2
24
DB0
DB15
X
8
923
22
FIRST 8 BITS ARE
DON’T CARE BITS
07
02
7-
0
03
Figure 3. Readback Mode Timing Diagram
SCLK
SDIN
24
2
1
DB0
SDO
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
UNDEFINED
INPUT WORD FOR DAC N
25
48
26
LATCH
t21
t22
t23
t24
t27
t28
t26
t29
t25
DB23
DB0
07
02
7-
00
4
Figure 4. Daisy-Chain Mode Timing Diagram
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