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參數(shù)資料
型號： AD5420AREZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 29/32頁
文件大小： 0K
描述： IC DAC 16BIT 1CH SER 24TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計資源： Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098)
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時間： 10µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 950mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm）裸露焊盤
供應(yīng)商設(shè)備封裝： 24-TSSOP 裸露焊盤
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電流，單極
采樣率（每秒）： *
AD5410/AD5420
Data Sheet
Rev. F | Page 6 of 32
AC PERFORMANCE CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 ; all specifications TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Current Settling Time2
10
s
16 mA step, to 0.1% FSR
40
s
16 mA step, to 0.1% FSR, L = 1 mH
AC PSRR
75
dB
200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage
1
Guaranteed by design and characterization; not production tested.
2
Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.
TIMING CHARACTERISTICS
AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, RLOAD = 300 ; all specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
WRITE MODE
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK low time
t3
13
ns min
SCLK high time
t4
13
ns min
LATCH delay time
t5
40
ns min
LATCH high time
t5
5
s min
LATCH high time after a write to the control register
t6
5
ns min
Data setup time
t7
5
ns min
Data hold time
t8
40
ns min
LATCH low time
t9
20
ns min
CLEAR pulse width
t10
5
s max
CLEAR activation time
READBACK MODE
t11
90
ns min
SCLK cycle time
t12
40
ns min
SCLK low time
t13
40
ns min
SCLK high time
t14
13
ns min
LATCH delay time
t15
40
ns min
LATCH high time
t16
5
ns min
Data setup time
t17
5
ns min
Data hold time
t18
40
ns min
LATCH low time
t19
35
ns max
Serial output delay time (CL SDO = 50 pF)4
t20
35
ns max
LATCH rising edge to SDO tristate
DAISY-CHAIN MODE
t21
90
ns min
SCLK cycle time
t22
40
ns min
SCLK low time
t23
40
ns min
SCLK high time
t24
13
ns min
LATCH delay time
t25
40
ns min
LATCH high time
t26
5
ns min
Data setup time
t27
5
ns min
Data hold time
t28
40
ns min
LATCH low time
t29
35
ns max
Serial output delay time (CL SDO = 50 pF)4
1
Guaranteed by characterization but not production tested.
2
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
4
CLSDO = capacitive load on SDO output.
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