AD5412/AD5422
Data Sheet
Rev. I | Page 36 of 44
DAC
IOUT
BOOST
CAP1
CAP2
C1
R1
C2
AVDD
4
k
12.5
k
4
0
0
69
9
6
-0
63
Figure 74. IOUT Filter Circuitry
0
5
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
10
15
20
25
O
U
T
P
U
T
C
U
RR
E
N
T
(m
A
)
TIME (ms)
TA = 25°C
AVDD = 24V
RLOAD = 300
0
6
9
6
-1
4
2
NO CAPACITOR
10nF ON CAP1
10nF ON CAP2
47nF ON CAP1
47nF ON CAP2
Figure 75. Slew Controlled 4 mA to 20 mA Output Current Step Using
External Capacitors on the CAP1 and CAP2 Pins
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
–1
0
1
2
3
4
5
6
7
8
O
UT
P
UT
CURRE
NT
(
mA)
TIME (ms)
TA = 25°C
AVDD = 24V
RLOAD = 300
NO EXTERNAL CAPS
10nF ON CAP1
10nF ON CAP2
06996-
043
Figure 76. Smoothing Out the Steps Caused by the Digital Slew
Rate Control Feature
Table 24. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range
Update Clock
Frequency (Hz)
Step Size (LSB)
1
2
4
8
16
32
64
128
257,730
0.25
0.13
0.06
0.03
0.016
0.008
0.004
0.0020
198,410
0.33
0.17
0.08
0.04
0.021
0.010
0.005
0.0026
152,440
0.43
0.21
0.11
0.05
0.027
0.013
0.007
0.0034
131,580
0.50
0.25
0.12
0.06
0.031
0.016
0.008
0.0039
115,740
0.57
0.28
0.14
0.07
0.035
0.018
0.009
0.0044
69,440
0.9
0.47
0.24
0.12
0.06
0.03
0.015
0.007
37,590
1.7
0.87
0.44
0.22
0.11
0.05
0.03
0.014
25,770
2.5
1.3
0.64
0.32
0.16
0.08
0.04
0.020
20,160
3.3
1.6
0.81
0.41
0.20
0.10
0.05
0.025
16,030
4.1
2.0
1.0
0.51
0.26
0.13
0.06
0.03
10,290
6.4
3.2
1.6
0.80
0.40
0.20
0.10
0.05
8280
7.9
4.0
2.0
1.0
0.49
0.25
0.12
0.06
6900
9.5
4.8
2.4
1.2
0.59
0.30
0.15
0.07
5530
12
5.9
3.0
1.5
0.74
0.37
0.19
0.09
4240
15
7.7
3.9
1.9
0.97
0.48
0.24
0.12
3300
20
9.9
5.0
2.5
1.24
0.62
0.31
0.16