參數(shù)資料
型號(hào): AD5405YCP
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface
中文描述: PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 12-BIT DAC, QCC40
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁(yè)數(shù): 5/24頁(yè)
文件大?。?/td> 925K
代理商: AD5405YCP
AD5405
TIMING CHARACTERISTICS
V
DD
= 2.5 V to 5.5 V, V
REF
= 5 V, I
OUT
2 = 0 V. All specifications T
MIN
to T
MAX,
unless otherwise noted.
Table 2.
Parameter
1, 2
Limit at T
MIN
, T
MAX
Unit
Write Mode
t
1
0
ns min
t
2
0
ns min
t
3
10
ns min
t
4
10
ns min
t
5
0
ns min
t
6
6
ns min
t
7
0
ns min
t
8
5
ns min
t
9
7
ns min
Data Readback Mode
t
10
0
ns typ
t
11
0
ns typ
t
12
5
ns typ
35
ns max
t
13
5
ns typ
10
ns max
Rev. 0 | Page 5 of 24
Conditions/Comments
R/W to CS setup time
R/W to CS hold time
CS low time
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
Address setup time
Address hold time
Data access time
Bus relinquish time
1
See
2
All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (V
IL
+ V
IH
)/2. Digital output timing measured
with load circuit in
.
Figure 3
Temperature range for Y version is 40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
Figure 2.
t
7
DATA VALID
t
6
t
2
CS
R/W
DATA
t
1
DATA VALID
t
2
t
13
t
12
t
3
t
8
t
9
DACA/DACB
t
4
t
5
t
11
t
10
0
Figure 2. Timing Diagram
I
OL
200
μ
A
I
OH
200
μ
A
C
50pF
TO
OUTPUT
PIN
V
OH (MIN)
+ V
OL (MAX)
2
0
Figure 3. Load Circuit for Data Timing Specifications
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