參數(shù)資料
型號(hào)： AD5405YCP
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface
中文描述： PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 12-BIT DAC, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁(yè)數(shù)： 17/24頁(yè)
文件大?。?/td> 925K
代理商： AD5405YCP
AD5405
Table 7. Suitable ADI Precision References Recommended for Use with AD5405 DACs
Reference
Output Voltage
Initial Tolerance
ADR01
10 V
0.1%
ADR02
5 V
0.1%
ADR03
2.5 V
0.2%
ADR425
5 V
0.04%
Table 8. Precision ADI Op Amps Suitable for Use with AD5405 DACs
Part No.
Max Supply Voltage V
OP97
±20
OP1177
±18
AD8551
+6
Table 9. High Speed ADI Op Amps Suitable for Use with AD5405 DACs
Part No.
Max Supply Voltage V
AD8065
±12
AD8021
±12
AD8038
±5
Rev. 0 | Page 17 of 24
Temperature Drift
3 ppm/°C
3 ppm/°C
3 ppm/°C
3 ppm/°C
0.1 Hz to 10 Hz noise
20 μV p-p
10 μV p-p
10 μV p-p
3.4 μV p-p
Package
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
V
OS
(max) μV
25
60
5
I
B
(max) nA
0.1
2
0.05
GBP MHz
0.9
1.3
1.5
Slew Rate V/μs
0.2
0.7
0.4
V
OS
(max) μV
1500
1000
3000
I
B
(max) nA
0.01
1000
0.75
BW @ A
CL
MHz
145
200
350
Slew Rate V/μs
180
100
425
PARALLEL INTERFACE
Data is loaded to the AD5405 in the format of a 12-bit parallel
word. Control lines CS and R/W allow data to be written to or
read from the DAC register. A write event takes place when CS
and R/W are brought low, data available on the data lines fills
the shift register, and the rising edge of CS latches the data and
transfers the latched data word to the DAC register. The DAC
latches are not transparent, thus a write sequence must consist
of a falling and rising edge on CS to ensure data is loaded to the
DAC register and its analog equivalent reflected on the DAC
output. A read event takes place when R/W is held high and CS
is brought low. Data is loaded from the DAC register back to the
input register and out onto the data line where it can be read
back to the controller for verification or diagnostic purposes.
The input and DAC registers of these devices are not trans-
parent, so a falling and rising edge of CS is required to load
each data-word.
MICROPROCESSOR INTERFACING
The AD5405 can be interfaced to a variety of 16-bit micro-
controllers or DSP processors. Figure 38 shows the AD5405
DAC interfaced to a generic 16-bit microcontroller/DSP
processor. Microprocessor interfacing to this family of DAC is
via a data bus that uses a standard protocol compatible with
microcontrollers and DSP processors. The address decoder
selects DAC A or DAC B and also to loads parallel data to the
input latch or to read data from the DAC using an AND gate.
AD54xx*
DAC A/B
CS
WR
DB0 TO DB11
A0 TO AX
MICRO/DSP*
WR
DB0 TO DB11
A
ADDRESS
DECODER
DATA BUS
ADDRESS BUS
A + 1
0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD54xx to Parallel Interface
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5405 is mounted should be designed so that the
analog and digital sections are separated, and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
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