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參數(shù)資料
| 型號(hào)： | AD5405YCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | Dual 12-Bit, High Bandwidth, Multiplying DAC with 4-Quadrant Resistors and Parallel Interface |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.015 us SETTLING TIME, 12-BIT DAC, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 925K |
| 代理商： | AD5405YCP |
AD5405
Stability
In the I-to-V configuration, the I
OUT
of the DAC and the
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response which can cause ringing or instability in the closed-
loop applications circuit.
Rev. 0 | Page 15 of 24
An optional compensation capacitor, C1, can be added in
parallel with R
FB
for stability, as shown in Figure 32 and
Figure 33. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for the compensation.
SINGLE-SUPPLY APPLICATIONS
Voltage Switching Mode of Operation
Figure 34 shows these DACs operating in the voltage switching
mode. The reference voltage, V
IN
, is applied to the I
OUT
1 pin,
I
OUT
2 is connected to AGND, and the output voltage is available
at the V
REF
terminal. In this configuration, a positive reference
voltage results in a positive output voltage, making single-
supply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance). Thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
V
OUT
V
DD
GND
V
IN
I
OUT
2
I
OUT
1
R
FB
V
DD
V
REF
R
2
R
1
0
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 34. Single-Supply Voltage Switching Mode
Note that V
IN
is limited to low voltages because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, V
IN
must not go negative by
more than 0.3 V or an internal diode turns on, exceeding the
max ratings of the device. In this type of application, the full
range of multiplying capability of the DAC is lost.
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the V
REF
polarity for dc reference voltages. In order to achieve a positive
voltage output, an applied negative reference to the input of
the DAC is preferred over the output inversion through an
inverting amplifier because of the resistor’s tolerance errors. To
generate a negative reference, the reference can be level shifted
by an op amp such that the V
OUT
and GND pins of the reference
become the virtual ground and 2.5 V respectively, as shown in
Figure 35.
V
OUT
= 0V TO +2.5V
V
DD
= +5V
GND
I
OUT
2
I
OUT
1
R
FB
V
DD
V
REF
C
1
GND
V
IN
V
OUT
ADR03
+
5V
–5V
1/2 AD8552
1/2 AD8552
12-BIT DAC
–2.5V
0
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 35. Positive Voltage Output with Minimum Components
ADDING GAIN
In applications where the output voltage is required to be
greater than V
IN
, gain can be added with an additional external
amplifier or it can also be achieved in a single stage. Consider
the effect of temperature coefficients of the thin film resistors
of the DAC. Simply placing a resistor in series with the R
FB
resistor causes mismatches in the temperature coefficients
resulting in larger gain temperature coefficient errors. Instead,
the circuit of Figure 36 is a recommended method of increasing
the gain of the circuit. R
1
, R
2
, and R
3
should all have similar
temperature coefficients, but they need not match the temper-
ature coefficients of the DAC. This approach is recommended
in circuits where gains of > 1 are required.
V
OUT
V
DD
GND
I
OUT
2
I
OUT
1
R
FB
V
DD
V
REF
C
1
12-BIT
DAC
R
3
R2
R2
V
IN
R1 = R2R3
R2 + R3
GAIN = R2 + R3
R2
0
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 36. Increasing Gain of Current Output DAC
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