參數(shù)資料
型號(hào)： AD5392BST-3
廠商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs
中文描述： SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP52
封裝： 10 X 10 MM, MS-026BCC, LQFP-52
文件頁(yè)數(shù)： 27/44頁(yè)
文件大小： 1319K
代理商： AD5392BST-3
AD5390/AD5391/AD5392
I
2
C SERIAL INTERFACE
The AD5390/AD5391/AD5392 products feature an I
2
C-
compatible 2-wire interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facilitate
communication between the DACs and the master at rates up
to 400 kHz. Figure 4 shows the 2-wire interface timing diagram.
Rev. A | Page 27 of 44
When selecting the I
2
C operating mode by configuring the
SPI/I
2
C pin to Logic 0, the device is connected to the I
2
C bus
as a slave device (that is, no clock is generated by the device).
The AD5390/AD5391/AD5392 have a 7-bit slave address
1010 1(AD1)(AD0). The five MSBs are hard-coded and the
two LSBs are determined by the state of the AD1 and AD0
pins. The hardware configuration facility for the AD1 and AD0
pins allows four of these devices to be configured on the bus.
I
2
C DATA TRANSFER
One data bit is transferred during each SCL clock cycle. The
data on SDA must remain stable during the high period of the
SCL clock pulse. Changes in SDA while SCL is high are control
signals that configure START and STOP Conditions. Both SDA
and SCL are pulled high by the external pull-up resistors when
the I
2
C bus is not busy.
START AND STOP CONDITIONS
A master device initiates communication by issuing a START
condition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA, while SCL is high. A START condition from
the master signals the beginning of a transmission to the
AD539x. The STOP condition frees the bus. If a repeated
START condition (Sr) is generated instead of a STOP condition,
the bus remains active.
REPEATED START CONDITION
A repeated START (Sr) condition may indicate a change of data
direction on the bus. Sr may be used when the bus master is
writing to several I
2
C devices and does not want to relinquish
control of the bus.
ACKNOWLEDGE BIT (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. An ACK is always generated by the receiving
device. The AD539x devices generate an ACK when receiving
an address or data by pulling SDA low during the ninth clock
period.
Monitoring the ACK allows for detection of unsuccessful data
transfers. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master should reattempt
communication.
AD539x SLAVE ADDRESSES
A bus master initiates communication with a slave device by
issuing a START condition followed by the 7-bit slave address.
When idle, the AD539x device waits for a START condition
followed by its slave address. The LSB of the address word is the
read/write (R/W) bit. The AD539x devices are receive devices
only, and R/W = 0 when communicating with them. After
receiving the proper address 1010 1(AD1) (AD0), the AD539x
issues an ACK by pulling SDA low for one clock cycle. The
AD539x has four user-programmable addresses determined by
the AD1 and AD0 bits.
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