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參數(shù)資料
| 型號： | AD5392BST-3 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 8-/16-Channel, 3 V/5 V, Serial Input, Single- Supply, 12-/14-Bit Voltage Output DACs |
| 中文描述： | SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP52 |
| 封裝： | 10 X 10 MM, MS-026BCC, LQFP-52 |
| 文件頁數(shù)： | 23/44頁 |
| 文件大?。?/td> | 1319K |
| 代理商： | AD5392BST-3 |
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AD5390/AD5391/AD5392
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5390/AD5391 are complete single-supply, 16-channel,
voltage output DACs offering a resolution of 14 bits and 12 bits,
respectively. The AD5392 is a complete single-supply, 8-channel,
voltage output DAC offering 14-bit resolution. All devices are
available in 64-lead LFCSP and 52-lead LQFP packages and
feature serial interfaces. This family includes an internal select-
able 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive
the buffered reference inputs (alternatively, an external refer-
ence can be used to drive these inputs). All channels have an on-
chip output amplifier with rail-to-rail output capable of driving
a 5 kΩ in parallel with a 200 pF load.
Rev. A | Page 23 of 44
The architecture of a single DAC channel consists of a 12-bit
and 14-bit resistor-string DAC followed by an output buffer
amplifier operating at a gain of 2. This resistor-string archi-
tecture guarantees DAC monotonicity. The 12-bit and 14-bit
binary digital code loaded to the DAC register deter-mines at
what node on the string the voltage is tapped off before being
fed to the output amplifier. Each channel on these devices con-
tains independent offset and gain control registers, allowing the
user to digitally trim offset and gain.
0
x1 INPUT
REG
m REG
c REG
x2
DAC
14-BIT
INPUT
DATA
R
R
AVDD
VOUT
VREF
Figure 31. AD5390/92 Single-Channel Architecture
These registers let the user calibrate out errors in the complete
signal chain including the DAC using the internal m and c
registers, which hold the correction factors. All channels are
double-buffered, allowing synchronous updating of all channels
using the LDAC pin. Figure 31 shows a block diagram of a
single channel on the AD5390/AD5391/AD5392.
The digital input transfer function for each DAC can be
represented as
(
)
(
)
1
2
1
2
/
(
2
+
×
+
=
n
n
c
x
m
x
where:
x
2 is the data-word loaded to the resistor-string DAC.
x
1 is the 12-bit and 14-bit data-word written to the DAC input
register.
m
is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE
on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB
of the gain coefficient is zero.
n
= DAC resolution (
n
= 14 for the AD5390/AD5392 and
n
= 12 for the AD5391).
c
is the 12-bit and 14-bit offset coefficient (default is 0x2000 on
the AD5390/AD5392 and 0x800 on the AD5391).
The complete transfer function for these devices can be
represented as
n
x
VREF
VOUT
2
/
2
×
×
=
where:
x
2 is the data-word loaded to the resistor-string DAC.
V
REF
is the reference voltage applied to the REFIN/REFOUT pin
on the DAC when an external reference is used, 2.5 V for
specified performance on the AD539x-5 products and 1.25 V
on the AD539x-3 products.
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| AD5392BSTZ-3 | 功能描述:IC DAC 14BIT 8CHAN 3V 52LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5392BSTZ-5 | 功能描述:IC DAC 14BIT 8CHAN 3V 52LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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