I2C SERIAL INTERFACE
參數(shù)資料
型號(hào)： AD5390BSTZ-5
廠商： Analog Devices Inc
文件頁數(shù)： 5/44頁
文件大?。?/td> 0K
描述： IC DAC 14BIT I2C 16CH 52-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5390/1/2 Redesign Change 16/May/2012
設(shè)計(jì)資源： 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029)
AD5390/91/92 Channel Monitor Function (CN0030)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 單電源
功率耗散（最大）： 35mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-LQFP（10x10）
包裝： 托盤
輸出數(shù)目和類型： 16 電壓，單極
采樣率（每秒）： 125k
產(chǎn)品目錄頁面： 782 (CN2011-ZH PDF)
配用： EVAL-AD5390EBZ-ND - BOARD EVALUATION FOR AD5390
Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 13 of 44
I2C SERIAL INTERFACE
DVDD = 2.7 V to 5.5 V; AVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 7. I2C Serial Interface1
Parameter2
Limit at TMIN, TMAX
Unit
Description
FSCL
400
kHz max
SCL clock frequency
t1
2.5
s min
SCL cycle time
t2
0.6
s min
tHIGH, SCL high time
t3
1.3
s min
tLOW, SCL low time
t4
0.6
s min
tHD, STA, start/repeated start condition hold time
t5
100
ns min
tSU, DAT, data setup time
t63
0.9
s max
tHD, DAT data hold time
0
s min
tHD, DAT data hold time
t7
0.6
s min
tSU, STA setup time for repeated start
t8
0.6
s min
tSU, STO stop condition setup time
t9
1.3
s min
tBUF, bus free time between a stop and a start condition
t10
300
ns max
tF, fall time of SDA when transmitting
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS-compatible)
t11
300
ns max
tF, fall time of SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS-compatible)
300
ns max
tF, fall time of SCL and SDA when receiving
20 + 0.1 CB
ns min
tF, fall time of SCL and SDA when transmitting
400
pF max
Capacitive load for each bus line
1
Guaranteed by design and characterization, not production tested.
2
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4
CB is the total capacitance of one bus line in pF; tR and tF measured between 0.3 DVDD and 0.7 DVDD.
SCL
SDA
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t9
t3
t10
t11
t4
t6
t2
t5
t7
t8
t1
03773-
007
Figure 6. I2C Interface Timing Diagram
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