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參數(shù)資料
| 型號： | AD5390BSTZ-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT I2C 16CH 52-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5390/1/2 Redesign Change 16/May/2012 |
| 設計資源： | 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029) AD5390/91/92 Channel Monitor Function (CN0030) |
| 標準包裝： | 1 |
| 設置時間： | 8µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 35mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設備封裝： | 52-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 16 電壓，單極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
| 配用： | EVAL-AD5390EBZ-ND - BOARD EVALUATION FOR AD5390 |
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AD5390/AD5391/AD5392
Data Sheet
Rev. E | Page 30 of 44
2-BYTE MODE
The 2-byte mode lets the user update channels sequentially
following initialization of this mode. The device address byte is
required only once and the address pointer is configured for
autoincrement or burst mode.
The user must begin with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF), which initiates the burst mode of opera-
tion. The address pointer initializes to Channel 0 and the data
following the pointer is loaded to Channel 0. The address
pointer automatically increments to the next address.
The REG0 and REG1 bits in the data byte determine the register
to be updated. In this mode, following the initialization, only
the two data bytes are required to update a channel. The
channel address automatically increments from Address 0 to
the final address and then returns to the normal 3-byte mode
of operation. This mode allows transmission of data to all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode of operation is not supported in
2-byte mode. Figure 36 shows a typical configuration.
REG0
MSB
LSB
REG1
1
0
A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1
1
AD1
AD0
R/W
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
START
CONDITION
BY
MASTER
ACK
BY
CONVERTER
ACK
BY
CONVERTER
ADDRESS BYTE
POINTER BYTE
CHANNEL 1 DATA
CHANNEL 0 DATA
CHANNEL N DATA FOLLOWED BY STOP
MSB
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
REG0
MSB
LSB
REG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
REG0
MSB
LSB
REG1
ACK
BY
CONVERTER
ACK
BY
CONVERTER
STOP
CONDITION
BY
MASTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
03773-
025
Figure 36. 2-Byte Mode I2C Write Operation
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相關代理商/技術參數(shù) |
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|---|---|
| AD5391BCP | 制造商:Analog Devices 功能描述:DAC HEXADECIMAL RES-STRING 12-BIT 64LFCSP - Bulk |
| AD5391BCP-3 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 12-bit 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8/16-CHANNEL, 14/12-BIT, 3V/5V VOLTAGE OUT DAC - Bulk |
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| AD5391BCP-3-REEL7 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 12-bit 64-Pin LFCSP EP T/R |
| AD5391BCP-5 | 制造商:Analog Devices 功能描述:DAC 16-CH Resistor-String 12-bit 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT DAC 16CH 5V 5391 LFCSP-64 |
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