參數(shù)資料
型號(hào)： AD5390BSTZ-5
廠商： Analog Devices Inc
文件頁數(shù)： 30/44頁
文件大?。?/td> 0K
描述： IC DAC 14BIT I2C 16CH 52-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5390/1/2 Redesign Change 16/May/2012
設(shè)計(jì)資源： 8 to 16 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5390/1/2 (CN0029)
AD5390/91/92 Channel Monitor Function (CN0030)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 16
電壓電源： 單電源
功率耗散（最大）： 35mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 52-LQFP
供應(yīng)商設(shè)備封裝： 52-LQFP（10x10）
包裝： 托盤
輸出數(shù)目和類型： 16 電壓，單極
采樣率（每秒）： 125k
產(chǎn)品目錄頁面： 782 (CN2011-ZH PDF)
配用： EVAL-AD5390EBZ-ND - BOARD EVALUATION FOR AD5390
AD5390/AD5391/AD5392
Data Sheet
Rev. E | Page 36 of 44
AD539x to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done
by writing to the synchronous serial port control register
(SSPCON)—see the PIC16/17 Microcontroller User Manual.
In Figure 38, I/O port RA1 is used to pulse SYNC and enable
the serial port of the AD539x. This microcontroller transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive read/write operations are needed,
depending on the mode. Figure 38 shows the connection
diagram.
DVDD
PIC16C6x/7x
AD539x
RESET
SDO
SDI/RC4
DIN
SDO/RC5
SCLK
SCK/RC3
RA1
SYNC
SPI/I2C
03
77
3-
0
27
Figure 38. AD539x to PIC16C6x/7x Interface
AD539x to 8051
The AD539x requires a clock synchronized to the serial data.
The 8051 serial interface must, therefore, be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 39 shows how the 8051 is
connected to the AD539x. Because the AD539x shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD539x
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.
DVDD
8xC51
SDO
DIN
AD539x
RESET
RxD
SCLK
TxD
P1.1
SYNC
SPI/I2C
0
37
73
-0
28
Figure 39. AD539x to 8051 Interface
Figure 40 shows a serial interface between the AD539x and
the SPORT transmit alternate framing mode. The ADSP2101
SPORT is programmed through the SPORT control register and
should be configured as follows: internal clock operation, active
low framing, and 16-bit word length. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled.
DVDD
ADSP2101
AD539x
RESET
DIN
DT
SDO
DR
SCLK
SCK
TFS
RFS
SYNC
SPI/I2C
0
3
773-
029
Figure 40. AD539x to ADSP2101 Interface
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