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| 型號： | AD5384BBC-5REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/32頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 40CH 5V 100-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5384 Models Discontinuation 15/May/2012 |
| 標準包裝： | 400 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 125k |
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AD5384
Data Sheet
Pin No.
Mnemonic
Description
A10
LDAC
Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents
of the input registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC
is taken low while BUSY is active and internal calculations are taking place, the LDAC event is stored,
and the DAC registers are updated when BUSY goes inactive. However, any events on LDAC during
power-on reset or at RESET are ignored.
A11
BUSY
Digital CMOS Output. BUSY goes low during internal calculations of the data (×2) loaded to the DAC
data register. During this time, the user can continue writing new data to the ×1, c, and m registers,
but no further updates to the DAC registers and DAC outputs can take place. If LDAC is taken low
while BUSY is low, this event is stored. BUSY also goes low during power-on reset, and when the
BUSY pin is low. During this time, the interface is disabled, and any events on LDAC are ignored.
A CLR operation also brings BUSY low.
B1
VOUT25
Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. The output is capable of driving an output load of 5 k to ground.
Typical output impedance is 0.5 .
B4
DIN/SDA
In serial interface mode, DIN acts as the serial data input. Data must be valid on the falling edge of
SCLK.
In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.
B5
SDO
Serial Data Output in Serial Interface Mode. Three-state CMOS output. SDO can be used for
daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge
of SCLK, and is valid on the falling edge of SCLK.
B8
SPI/I2C
Serial Interface Mode Select. This is a multifunction pin. When this pin is high, SPI mode is selected.
When this pin is low, I2C is selected.
B9
RESET
Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to
that of the power-on reset generator. When this pin is taken low, the state machine initiates a reset
sequence to digitally reset the ×1, m, c, and ×2 registers to their default power-on values. This
sequence typically takes 270 s. The falling edge of RESET initiates the RESET process, and BUSY
goes low for the duration, returning high when RESET is complete. While BUSY is low, all interfaces
are disabled, and all LDAC pulses are ignored. When BUSY returns high, the device resumes normal
operation, and the status of the RESET pin is ignored until the next falling edge is detected.
B10
VOUT22
Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. The output is capable of driving an output load of 5 k to ground.
Typical output impedance is 0.5 .
B12, C1
VOUT23,
VOUT26
Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating
at a gain of 2. Each output is capable of driving an output load of 5 k to ground.
Typical output impedance is 0.5 .
C2, D2
SIGNAL_GND4
Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are
connected together internally and must be connected to the AGND plane as close as possible to the
C12, D1
VOUT21,
VOUT27
Buffered Analog Outputs. Each analog output is driven by a rail-to-rail output amplifier operating
at a gain of 2. Each output is capable of driving an output load of 5 k to ground.
Typical output impedance is 0.5 .
D4, E4
DAC_GND4
Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for
the internal 14-bit DAC. Connect these pins to the AGND plane.
D5
AGND4
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect
all AGND pins externally to the AGND plane.
D8
AGND3
Analog Ground Reference Point. Each group of eight channels contains an AGND pin. Connect
all AGND pins externally to the AGND plane.
D9, E9
DAC_GND3
Each Group of Eight Channels Contains a DAC_GNDx Pin. This is the ground reference point for
the internal 14-bit DAC. Connect these pins to the AGND plane.
D11
VOUT20
Buffered Analog Output. The analog output is driven by a rail-to-rail output amplifier operating at a
gain of 2. The output is capable of driving an output load of 5 k to ground.
Typical output impedance is 0.5 .
D12, E1
AVDD3, AVDD4
Analog Supply Pins. Each group of eight channels has a separate AVDDx pin. Short these pins
internally and decouple them with a 0.1 F ceramic capacitor and a 10 F tantalum capacitor.
Operating range is 4.5 V to 5.5 V.
E2, F2
SIGNAL_GND1
Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GNDx pins are
connected together internally and must be connected to the AGND plane as close as possible to the
Rev. B | Page 12 of 32
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| AD5384BBCZ-3 | 功能描述:IC DAC 14BIT 40CH 5V 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD5384BBCZ-5 | 功能描述:IC DAC 14BIT 40CH 5V 100-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
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