參數(shù)資料
型號(hào)： AD5384BBC-5REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/32頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 40CH 5V 100-CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5384 Models Discontinuation 15/May/2012
標(biāo)準(zhǔn)包裝： 400
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 40
電壓電源： 單電源
功率耗散（最大）： 80mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 40 電壓，單極
采樣率（每秒）： 125k
Data Sheet
AD5384
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE—GENERAL
The AD5384 is a complete single-supply, 40-channel, voltage
output DAC offering 14-bit resolution, available in a 100-lead
CSP_BGA package. It features two serial interfaces, SPI and
I2C. This family includes an internal 1.25 V/2.5 V, 10 ppm/°C
that drives the buffered reference inputs. Alternatively, an
external reference can drive these inputs. Reference selection is
via a bit in the control register. Internal/external reference
selection is via the CR10 bit in the control register, and the
CR12 bit in the control register selects the reference magnitude
if the internal reference is selected. All channels have an on-chip
output amplifier with rail-to-rail output capable of driving 5 k
in parallel with a 200 pF load.
The architecture of a single DAC channel consists of a 14-bit
resistor string DAC followed by an output buffer amplifier
operating at a gain of 2. This resistor string architecture
guarantees DAC monotonicity. The 14-bit binary digital code
loaded to the DAC register determines at which node on the
string the voltage is tapped off before being fed to the output
amplifier.
Each channel on these devices contains independent offset and
gain control registers allowing the user to digitally trim offset
and gain. These registers let the user calibrate out errors in the
complete signal chain, including the DAC, using the internal m
and c registers that hold the correction factors. All channels are
double buffered, allowing synchronous updating of all channels
using the LDAC pin. Figure 24 shows a block diagram of a
single channel on the AD5384. The following represents the
digital input transfer function for each DAC:
x2 = [(m + 2)/ 2n× x1] + (c – 2n– 1)
where:
x2 is the data-word loaded to the resistor-string DAC.
x1 is the 14-bit data-word written to the DAC input register.
m is the gain coefficient (default is 0x3FFE on the AD5384).
The gain coefficient is written to the 13 most significant bits
(DB13 to DB1) and the LSB (DB0) is 0.
n is the DAC resolution (n = 14 for AD5384).
c is the14-bit offset coefficient (default is 0x2000).
VOUTx
R
14-BIT
DAC
m REG
c REG
×1 INPUT
REG
×2
INPUT DATA
VREF (+)
AVDDx
AGND
04652-
026
Figure 24. Single-Channel Architecture
The following represents the complete transfer function for
these devices:
VOUT = 2 × VREF × x2/2n
where:
x2 is the data-word loaded to the resistor string DAC.
VREF is the internal reference voltage or the reference voltage
externally applied to the DAC REF_OUT/REF_IN pin. For
specified performance, an external reference voltage of 2.5 V is
recommended.
DATA DECODING
The AD5384 contains a 14-bit data bus, DB13 to DB0.
Depending on the value of REG1 and REG0 outlined in Table 7,
this data is loaded into the addressed DAC input register(s),
offset (c) register(s), or gain (m) register(s). Table 8, Table 9,
and Table 10 outline the contents of the format data, offset (c),
and gain (m) registers.
Table 7. Register Selection
REG1
REG0
Register Selected
1
Input data register (×1)
1
0
Offset register (c)
0
1
Gain register (m)
0
Special function registers (SFRs)
Table 8. DAC Data Format (REG1 = 1, REG0 = 1)
DB13 to DB0
DAC Output (V)
11
1111
2 VREF × (16383/16384)
11
1111
1110
2 VREF × (16382/16384)
10
0000
0001
2 VREF × (8193/16384)
10
0000
2 VREF × (8192/16384)
01
1111
2 VREF × (8191/16384)
00
0000
0001
2 VREF × (1/16384)
00
0000
0
Table 9. Offset Data Format (REG1 = 1, REG0 = 0)
DB13 to DB0
Offset (LSB)
11
1111
+8191
11
1111
1110
+8190
10
0000
0001
+1
10
0000
0
01
1111
–1
00
0000
0001
–8191
00
0000
–8192
Table 10. Gain Data Format (REG1 = 0, REG0 = 1)
DB13 to DB0
Gain Factor
11
1111
1110
1
10
1111
1110
0.75
01
1111
1110
0.5
00
1111
1110
0.25
00
0000
0
Rev. B | Page 19 of 32
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