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| 型號： | AD5384BBC-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CH 5V 100-CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5384 Models Discontinuation 15/May/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
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AD5384
Data Sheet
I2C SERIAL INTERFACE
of a serial data line (SDA) and a serial clock line (SCL). SDA and
SCL facilitate communication between the AD5384 and the master
at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing
diagrams that incorporate three different modes of operation.
Select I2C mode by configuring the SPI/I2C pin to a Logic 0. The
device is connected to this bus as a slave device, and no clock is
generated by the AD5384. The AD5384 has a 7-bit slave address,
1010 1 (AD1)(AD0) The 5 MSBs are hard coded, and the two LSBs
are determined by the state of the AD1 and AD0 pins. The ability
to hardware-configure AD1 and AD0 allows four of these devices
to be configured on the bus.
I2C Data Transfer
During each SCL clock cycle, one data bit transfers. The data on
SDA must remain stable during the high period of the SCL clock
pulse. Changes in SDA while SCL is high are control signals that
configure start and stop conditions. When the I2C bus is not busy,
the external pull-up resistors pull both SDA and SCL high.
Start and Stop Conditions
A master device initiates communication by issuing a start
condition. A start condition is a high to low transition on SDA with
SCL high. A stop condition is a low to high transition on SDA
while SCL is high. A start condition from the master signals the
beginning of a transmission to the AD5384. The stop condition
frees the bus. If a repeated start condition (Sr) generates instead of a
stop condition, the bus remains active.
Repeated Start Conditions
A repeated start (Sr) condition can indicate a change of data
direction on the bus. Use Sr when the bus master is writing to
several I2C devices and wants to maintain control of the bus.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to any
8-bit data-word. ACK is always generated by the receiving device.
The AD5384 devices generate an ACK when receiving an address
or data by pulling SDA low during the ninth clock period.
Monitoring ACK allows detection of unsuccessful data transfers.
An unsuccessful data transfer occurs if a receiving device is busy or
if a system fault occurs. In the event of an unsuccessful data
transfer, the bus master reattempts communication.
Slave Addresses
A bus master initiates communication with a slave device by
issuing a start condition, followed by the 7-bit slave address.
When idle, the AD5384 waits for a start condition followed by its
slave address. The LSB of the address word is the read/write (R/W)
bit. The AD5384 devices are receive-only devices; when
communicating with these, R/W = 0. After receiving the proper
address 1010 1(AD1)(AD0), the AD5384 issues an ACK by pulling
SDA low for one clock cycle.
The AD5384 has four different user programmable addresses
determined by the AD1 and AD0 bits.
Write Operation
Data can be written to the AD5384 DACs in three modes: 4-byte
mode, 3-byte mode, and 2-byte mode.
4-Byte Mode
When writing to the AD5384 DACs, the user must begin with an
address byte (R/W = 0), after which the DAC acknowledges that it
is prepared to receive data by pulling SDA low. The address byte is
followed by the pointer byte; this addresses the specific channel in
the DAC to be addressed and also is acknowledged by the DAC.
Two bytes of data are then written to the DAC, as shown in
Figure 27. A stop condition follows. This lets the user update a
single channel within the AD5384 at any time, and requires four
bytes of data to transfer from the master.
1
0
1
0
1
AD1
AD0
R/W
0
A5
A4
A3
A2
A1
A0
SCL
SDA
SCL
SDA
START COND
BY MASTER
ACK BY
AD538x
ACK BY
AD538x
ADDRESS BYTE
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
POINTER BYTE
MSB
ACK BY
AD538x
ACK BY
AD538x
STOP
COND
BY
MASTER
REG1
REG0
MSB
LSB
MSB
LSB
04652-
029
Figure 27. 4-Byte, I2C Write Operation
Rev. B | Page 26 of 32
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