參數(shù)資料
型號(hào)： AD5384BBC-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/32頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 40CH 5V 100-CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5384 Models Discontinuation 15/May/2012
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 40
電壓電源： 單電源
功率耗散（最大）： 80mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 100-CSBGA（10x10）
包裝： 托盤
輸出數(shù)目和類型： 40 電壓，單極
采樣率（每秒）： 125k
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
AD5384
Data Sheet
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5384 contains a number of special function registers
(SFRs), as outlined in Table 11. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using Address Bits A5 to A0.
Table 11. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
A5
A4
A3
A2
A1
A0
Function
X
0
No operation (NOP)
0
1
Write CLR code
0
1
0
Soft CLR
0
1
0
Soft power-down
0
1
0
1
Soft power-up
0
1
0
Control register write
1
0
1
0
Control register read
0
1
0
1
0
Monitor channel
0
1
Software reset
SFR COMMANDS
NOP (No Operation)
REG1 = REG0 = 0, and A5 to A0 = 000000.
Performs no operation but is useful in serial readback mode to
clock out data on DOUT for diagnostic purposes. BUSY pulses
low during an NOP operation.
Write CLR Code
REG1 = REG0 = 0, A5 to A0 = 000001, and DB13 to DB0 =
contains the CLR data.
Bringing the CLR line low, or exercising the soft clear function,
loads the contents of the DAC registers, with the data contained
in the user configurable CLR register, and sets VOUT0 to
VOUT39, accordingly. This is very useful for setting up a
specific output voltage in a clear condition. It is also beneficial
for calibration purposes; the user can load full scale or zero
scale to the clear code register and then issue a hardware or
software clear to load this code to all DACs, removing the need
for individual writes to each DAC. Default at power-up is all 0s.
Soft CLR
REG1 = REG0 = 0, A5 to A0 = 000010, and DB13 to DB0 =
don’t care.
Executing this instruction performs the CLR, which is
functionally the same as that provided by the external CLR pin.
The DAC outputs are loaded with the data in the CLR code
register. It takes 35 s to execute fully the SOFT CLR, as
indicated by the BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A5 to A0 = 001000, and DB13 to DB0 =
don’t care.
Executing this instruction performs a global power-down that
puts all channels in low power mode, reducing the analog
supply current to 2 A maximum, and the digital current to
20 A maximum. In power-down mode, the output amplifier
can be configured as a high impedance output or can provide a
100 k load to ground. The contents of all internal registers are
retained in power-down mode. While in power-down mode, no
registers can be written to.
Soft Power-Up
REG1 = REG0 = 0, A5 to A0 = 001001, and DB13 to DB0 =
don’t care.
This instruction powers up the output amplifiers and the
internal reference. The time to exit power-down is 8 s. The
hardware power-down and software functions are internally
combined in a digital OR function.
Software Reset
REG1 = REG0 = 0, A5 to A0 = 001111, and DB13 to DB0 =
don’t care.
This instruction implements a software reset. All internal
registers reset to their default values, which correspond to m at
full scale and c at zero. The contents of the DAC registers clear,
setting all analog outputs to 0 V. The soft reset activation time is
135 s. Only perform a soft reset when the AD5384 is not in
power-down mode.
Rev. B | Page 20 of 32
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