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參數(shù)資料
| 型號： | AD5384BBC-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CH 5V 100-CSPBGA |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | AD5384 Models Discontinuation 15/May/2012 |
| 標準包裝： | 1 |
| 設置時間： | 8µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 40 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 80mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應商設備封裝： | 100-CSBGA（10x10） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 40 電壓，單極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
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Data Sheet
AD5384
Table 12. Control Register Contents
MSB
LSB
CR13
CR12
CR11
CR10
CR9
CR8
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
Control Register Write/Read
REG1 = REG0 = 0, A5 to A0 = 001100, and R/W status
determines if the operation is a write (R/W = 0) or a read (R/W
= 1). The DB13 to DB0 bits contain the control register data.
Control Register Contents
CR13: power-down status. This bit configures the output
amplifier state in power-down mode This bit is configured as
follows:
For CR13 = 1, the amplifier output is high impedance
(default at power-up).
For CR13 = 0, the amplifier output is 100 k to ground.
CR12: REF select. This bit selects the operating internal
reference for the AD5384. CR12 is programmed as follows:
For CR12 = 1, the internal reference is 2.5 V, which is the
recommended operating reference.
For CR12 = 0, the internal reference is 1.25 V.
CR11: current boost control. This bit boosts the current in the
output amplifier, thereby altering its slew rate. This bit is
configured as follows:
For CR11 = 1, boost mode is on, maximizing the bias
current in the output amplifier, and optimizing its slew
rate but increasing the power dissipation.
For CR11 = 0, boost mode is off (default at power-up),
reducing the bias current in the output amplifier and the
overall power consumption.
CR10: internal/external reference. This bit determines if the
DAC uses its internal reference or an externally applied
reference. This bit is configured as follows:
For CR10 = 1, the internal reference is enabled. The
reference output depends on data loaded to CR12.
For CR10 = 0, the external reference is selected (default
at power-up).
CR9: channel monitor enable (see Channel Monitor Function).
This bit is configured as follows:
For CR9 = 1, the monitor is enabled which enables the
channel monitor function. After a write to the monitor
channel in the SFR register, the selected channel output
routes to the MON_OUT pin. VOUT39 operates as the
MON_OUT pin.
For CR9 = 0, the monitor is disabled (default at power-
up). When the monitor is disabled, the MON_OUT pin
assumes its normal DAC output function.
CR8: thermal monitor function. This function monitors the
AD5384 internal die temperature, when enabled. The thermal
monitor powers down the output amplifiers when the
temperature exceeds 130°C. This function protects the device
when power dissipation is exceeded, if a number of output
channels are simultaneously short circuited. If the die
temperature drops below 130°C, a soft power-up reenables the
output amplifiers. This bit is configured as follows:
For CR8 = 1, the thermal monitor is enabled.
For CR8 = 0, the thermal monitor is disabled (default at
power-up).
CR7: don’t care.
CR6 to CR2: toggle function enable. This function toggles the
output between two codes loaded to the A and B register for
each DAC. Control Register Bit CR6 to Control Register Bit
CR2 enable individual groups of eight channels for operation in
toggle mode. A Logic 1, written to any bit, enables a group of
channels, and a Logic 0 disables a group. LDAC is used to toggle
between the two registers. Table 13 shows the decoding for
toggle mode operation. For example, CR6 controls group w,
which contains Channel 32 to Channel 39, CR6 = 1 enables
these channels.
CR1 and CR0: don’t care.
Table 13. Toggle Function Enable
CR Bit
Group
Channels
CR6
4
32 to 39
CR5
3
24 to 31
CR4
2
16 to 23
CR3
1
8 to 15
CR2
0
0 to 7
Channel Monitor Function
REG1 = REG0 = 0, A5 to A0 = 001010, and DB13 to DB8 =
contain data to address the monitored channel.
The AD5384 has a channel monitor function that consists of a
multiplexer address via the interface, allows any channel output
to be routed to the MON_OUT pin for monitoring, using an
external ADC. In channel monitor mode, VOUT39 becomes
the MON_OUT pin, to which all monitored pins are routed.
Enable the channel monitor function in the control register
before any channels are routed to the MON_OUT pin. On the
AD5384, DB13 to DB8 contain the channel address for the
monitored channel. Selecting Channel Address 63 three-states
the MON_OUT pin.
Rev. B | Page 21 of 32
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