參數(shù)資料
型號(hào)： AD5382BSTZ-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/40頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT 32CH 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： Redesign Change 28/Oct/2011
設(shè)計(jì)資源： 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011)
AD5382 Channel Monitor Function (CN0012)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 14
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 單電源
功率耗散（最大）： 65mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤(pán)
輸出數(shù)目和類型： 32 電壓，單極
采樣率（每秒）： 125k
AD5382
Data Sheet
Rev. C | Page 30 of 40
2-Byte Mode
Following initialization of 2-byte mode, the user can update
channels sequentially. The device address byte is required only
once, and the pointer address pointer is configured for auto-
increment or burst mode.
The user must begin with an address byte (R/W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF) that initiates the burst mode of operation.
The address pointer initializes to Channel 0, the data following
the pointer is loaded to Channel 0, and the address pointer
automatically increments to the next address.
The REG0 and REG1 bits in the data byte determine which
register is updated. In this mode, following the initialization,
only the two data bytes are required to update a channel. The
channel address automatically increments from Address 0 to
Channel 31 and then returns to the normal 3-byte mode of
operation. This mode allows transmission of data to all channels
in one block and reduces the software overhead in configuring all
channels. A stop condition at any time exits this mode. Toggle
mode is not supported in 2-byte mode. Figure 32 shows a
typical configuration.
PARALLEL INTERFACE
The SER/PAR pin must be tied low to enable the parallel
interface and disable the serial interfaces. Figure 7 shows the
timing diagram for a parallel write. The parallel interface is
controlled by the following pins.
CS Pin
Active low device select pin.
WR Pin
On the rising edge of WR, with CS low, the addresses on Pins
A4 to A0 are latched; data present on the data bus is loaded into
the selected input registers.
REG0, REG1 Pins
The REG0 and REG1 pins determine the destination register of
the data being written to the AD5382. See Table 10.
Pins A4 to A0
Each of the 40 DAC channels can be addressed individually.
Pins DB13 to DB0
The AD5382 accepts a straight 14-bit parallel word on DB13 to
DB0, where DB13 is the MSB and DB0 is the LSB.
1
0
1
0
1
AD1
AD0
R/W
A7 = 1
A6 = 1
A5 = 1
A4 = 1
A3 = 1
A2 = 1
A1 = 1
A0 = 1
START COND
BY MASTER
ADDRESS BYTE
POINTER BYTE
MOST SIGNIFICANT DATA BYTE
CHANNEL 0 DATA
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
MSB
ACK BY
CONVERTER
ACK BY
AD538x
ACK BY
AD538x
MOST SIGNIFICANT DATA BYTE
CHANNEL 1 DATA
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
ACK BY
CONVERTER
MOST SIGNIFICANT DATA BYTE
CHANNEL N DATA FOLLOWED BY STOP
LEAST SIGNIFICANT DATA BYTE
ACK BY
CONVERTER
ACK BY
CONVERTER
STOP
COND
BY
MASTER
REG1
REG0
MSB
LSB
MSB
LSB
REG1
REG0
MSB
LSB
MSB
LSB
REG1
REG0
MSB
LSB
MSB
LSB
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
03733-
033
Figure 32. 2-Byte, I2C Write Operation
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