參數資料
| 型號： | AD5382BSTZ-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 18/40頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 32CH 5V 100-LQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 產品變化通告： | Redesign Change 28/Oct/2011 |
| 設計資源： | 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5382 (CN0011) AD5382 Channel Monitor Function (CN0012) |
| 標準包裝： | 1 |
| 設置時間： | 8µs |
| 位數： | 14 |
| 數據接口： | 串行，并聯(lián) |
| 轉換器數目： | 32 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 65mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 輸出數目和類型： | 32 電壓，單極 |
| 采樣率（每秒）： | 125k |
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Data Sheet
AD5382
Rev. C | Page 25 of 40
HARDWARE FUNCTIONS
RESET FUNCTION
Bringing the RESET line low resets the contents of all internal
registers to their power-on reset state. Reset is a negative edge-
sensitive input. The default corresponds to m at full scale and
to c at zero scale. The contents of the DAC registers are cleared,
setting VOUT0 to VOUT31 to 0 V. This sequence takes 270 s
max. The falling edge of RESET initiates the reset process;
BUSY goes low for the duration, returning high when RESET is
complete. While BUSY is low, all interfaces are disabled and all
LDAC pulses are ignored. When BUSY returns high, the part
resumes normal operation and the status of the RESET pin is
ignored until the next falling edge is detected.
ASYNCHRONOUS CLEAR FUNCTION
Bringing the CLR line low clears the contents of the DAC
registers to the data contained in the user-configurable CLR
register and sets VOUT0 to VOUT31 accordingly. This func-
tion can be used in system calibration to load zero scale and
full scale to all channels. The execution time for a CLR is 35 s.
BUSY AND LDAC FUNCTIONS
BUSY is a digital CMOS output that indicates the status of the
AD5382. The value of x2, the internal data loaded to the DAC
data register, is calculated each time the user writes new data to
the corresponding x1, c, or m register. During the calculation of
x2, the BUSY output goes low. While BUSY is low, the user can
continue writing new data to the x1, m, or c register, but no
DAC output updates can take place. The DAC outputs are
updated by taking the LDAC input low. If LDAC goes low while
BUSY is active, the LDAC event is stored and the DAC outputs
update immediately after BUSY goes high. The user may hold
the LDAC input permanently low, in which case the DAC
outputs update immediately after BUSY goes high. BUSY also
goes low during power-on reset and when a falling edge is
detected on the RESET pin. During this time, all interfaces are
disabled and any events on LDAC are ignored.
The AD5382 contains an extra feature whereby a DAC register
is not updated unless its x2 register has been written to since the
last time LDAC was brought low. Normally, when LDAC is
brought low, the DAC registers are filled with the contents of
the x2 registers. However, the AD5382 updates the DAC register
only if the x2 data changes, thereby removing unnecessary
digital crosstalk.
FIFO OPERATION IN PARALLEL MODE
The AD5382 contains a FIFO to optimize operation when
operating in parallel interface mode. The FIFO EN pin (level
sensitive, active high) is used to enable the internal FIFO. When
connected to DVDD, the internal FIFO is enabled, allowing the
user to write to the device at full speed. FIFO is only available in
parallel interface mode. The status of the FIFO EN pin is sam-
pled on power-up, and after a CLEAR or RESET, to determine if
the FIFO is enabled. In either serial or I2C interface mode, FIFO
EN should be tied low. Up to 128 successive instructions can be
written to the FIFO at maximum speed in parallel mode. When
the FIFO is full, further writes to the device are ignored. Figure
28 shows a comparison between FIFO mode and non-FIFO
mode in terms of channel update time. Figure 28 also shows
digital loading time.
NUMBER OF WRITES
TIME
(
s)
1
4
7
10
13
16
19
22
25
28
31
34
37
0
10
5
15
25
20
40
WITHOUT FIFO
(CHANNEL UPDATE TIME)
WITH FIFO
(CHANNEL UPDATE TIME)
WITH FIFO
(DIGITAL LOADING TIME)
03733
-0
29
Figure 28. Channel Update Rate (FIFO vs. Non-FIFO)
POWER-ON RESET
The AD5382 contains a power-on reset generator and a state
machine. The power-on reset resets all registers to a predefined
state and configures the analog outputs as high impedance.
The BUSY pin goes low during the power-on reset sequencing,
preventing data writes to the device.
POWER-DOWN
The AD5382 contains a global power-down feature, which puts
all channels into a low power mode and reduces the analog
power consumption to 2 A max and digital power consump-
tion to 20 A max. In power-down mode, the output amplifier
can be configured as a high impedance output or provide a
100 k load to ground. The contents of all internal registers are
retained in power-down mode. When exiting power-down, the
settling time of the amplifier elapses before the outputs settle to
their correct values.
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| AD5383BST | 制造商:Analog Devices 功能描述:- Bulk |
| AD5383BST-3 | 制造商:Rochester Electronics LLC 功能描述:32/40-CHANNEL 3V/5V SINGLE SUPPLY 12/14-BIT VOUT DAC - Bulk 制造商:Analog Devices 功能描述: |
| AD5383BST-5 | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 12-bit 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:32-CHN 5V SINGLE SUPPLY 12-BIT VOUT I.C. - Bulk |
| AD5383BST-5-REEL | 制造商:Analog Devices 功能描述:DAC 32-CH Resistor-String 12-bit 100-Pin LQFP T/R |
| AD5383BSTZ-3 | 功能描述:IC DAC 12BIT 32CHAN 3V 100LQFP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數:12 數據接口:串行，SPI? 轉換器數目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
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