參數(shù)資料
型號： AD5381BSTZ-5-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 25/40頁
文件大?。?/td> 0K
描述： IC DAC 12BIT 40CH 5V 100-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告： AD5381,3 Redesign Change 24/Oct/2011
設(shè)計資源： 40 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5381 (CN0010)
AD5381 Channel Monitor Function (CN0013)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時間： 6µs
位數(shù)： 12
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 40
電壓電源： 單電源
功率耗散（最大）： 80mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型： 40 電壓，單極
采樣率（每秒）： 167k
其它名稱： AD5381BSTZ-5-REELDKR
Data Sheet
AD5381
Rev. D | Page 31 of 40
MICROPROCESSOR INTERFACING
Parallel Interface
The AD5381 can be interfaced to a variety of 16-bit microcon-
trollers or DSP processors. Figure35 shows the AD5381 family
interfaced to a generic16-bit microcontroller/DSP processor.
The lower address lines fromthe processor areconnected to A0
to A5 on the AD5381. The upper address lines aredecoded to
provide a CS, LDACsignal for the AD5381. The fast interface
timing of the AD5381 allows direct interface to a wide variety
of microcontrollersand DSPs, as shown in Figure 35.
AD5381 to MC68HC11
The serial peripheral interface (SPI)on the MC68HC11 is
configured for master mode (MSTR = 1), clock polarity bit
(CPOL)= 0, and the clock phase bit (CPHA)= 1. The SPI is
configured by writing to the SPI control register (SPCR)—see
the MC68HC11 user manual. SCK of the MC68HC11 drives the
SCLK of the AD5381, the MOSIoutput drivesthe serial data
line (D
IN) of the AD5381, and the MISO input is driven from
D
OUT. The SYNC signal is derived from a port line (PC7).
When data is being transmitted to the AD5381, the SYNC line
is taken low (PC7). Data appearing on the MOSIoutput is valid
on the falling edge of SCK. Serial data from the MC68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle.
03731-034
MC68HC11
AD5381
MISO
MOSI
SCK
PC7
SDO
RESET
SER/PAR
DIN
SCLK
SYNC
SPI/I2C
DVDD
Figure 34. AD5381-to-MC68HC11 Interface
03732-035
CONTROLLER/
DSP PROCESSOR1
AD5381
ADDRESS
DECODE
UPPER BITS OF
ADDRESS BUS
DATA
BUS
A5
D15
D0
A4
A3
A2
A1
A0
R/W
A5
A4
A3
A2
A1
A0
WR
REG1
REG0
D11
D0
CS
LDAC
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 35. AD5381-to-Parallel Interface
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