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參數(shù)資料
| 型號： | AD5381BST-5 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 32-Channel, 3 V/5 V, Single-Supply, 14-Bit, Voltage Output DAC |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 6 us SETTLING TIME, 12-BIT DAC, PQFP100 |
| 封裝： | 14 X 14 MM, MS-026-BED, LQFP-100 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 1200K |
| 代理商： | AD5381BST-5 |
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AD5381
ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)
The AD5381 contains a number of special function registers
(SFRs), as outlined in Table 15. SFRs are addressed with
REG1 = REG0 = 0 and are decoded using address bits A5 to A0.
Rev. A | Page 22 of 36
Table 15. SFR Register Functions (REG1 = 0, REG0 = 0)
R/W
A5
A4
A3
A2
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
1
1
SFR COMMANDS
NOP (No Operation)
A1
0
0
1
0
0
0
0
1
1
A0
0
1
0
0
1
0
0
0
1
Function
NOP (No Operation)
Write CLR Code
Soft CLR
Soft Power-Down
Soft Power-Up
Control Register Write
Control Register Read
Monitor Channel
Soft Reset
REG1 = REG0 = 0, A5–A0 = 000000
Performs no operation but is useful in serial readback mode to
clock out data on D
OUT
for diagnostic purposes. BUSY pulses
low during a NOP operation.
Write CLR Code
REG1 = REG0 = 0, A5–A0 = 000001
DB11–DB0 = Contain the CLR data
Bringing the CLR line low or exercising the soft clear function
will load the contents of the DAC registers with the data con-
tained in the user configurable CLR register, and will set
VOUT0 to VOUT39 accordingly. This can be very useful for
setting up a specific output voltage in a clear condition. It is also
beneficial for calibration purposes; the user can load full scale
or zero scale to the clear code register and then issue a hard-
ware or software clear to load this code to all DACs, removing
the need for individual writes to each DAC. Default on power-
up is all zeros.
Soft CLR
REG1 = REG0 = 0, A5–A0 = 000010
DB11–DB0 = Don’t Care
Executing this instruction performs the CLR, which is function-
ally the same as that provided by the external CLR pin. The
DAC outputs are loaded with the data in the CLR code register.
It takes 35 μs to fully execute the SOFT CLR, as indicated by the
BUSY low time.
Soft Power-Down
REG1 = REG0 = 0, A5–A0 = 001000
DB11–DB0 = Don’t Care
Executing this instruction performs a global power-down
feature that puts all channels into a low power mode that
reduces the analog supply current to 2 μA max and the digital
current to 20 μA max. In power-down mode, the output
amplifier can be configured as a high impedance output or
provide a 100 k load to ground. The contents of all internal
registers are retained in power-down mode. No register can be
written to while in power-down.
Soft Power-Up
REG1 = REG0 = 0, A5–A0 = 001001
DB11–DB0 = Don’t Care
This instruction is used to power up the output amplifiers and
the internal reference. The time to exit power–down is 8 μs. The
hardware power-down and software function are internally
combined in a digital OR function.
Soft RESET
REG1 = REG0 = 0, A5–A0 = 001111
DB11–DB0 = Don’t Care
This instruction is used to implement a software reset. All
internal registers are reset to their default values, which
correspond to m at full scale and c at zero. The contents of the
DAC registers are cleared, setting all analog outputs to 0 V. The
soft reset activation time is 135 μs.
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