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參數(shù)資料
型號(hào): AD5330BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 28/28頁
文件大?。?/td> 0K
描述: IC DAC 8BIT SNGL VOUT 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 75
設(shè)置時(shí)間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 9 of 28
BUFFER
12-BIT
DAC
REGISTER
INPUT
REGISTER
POWER-DOWN
LOGIC
CS
WR
CLR
LDAC
VREF
VDD
VOUT
PD
GND
AD5340
POWER-ON
RESET
12
11
9
8
4
14
5
13
7
06
85
2-
007
DB10
DB9
DB0
..
15
24
1
DB11 2
BUF 3
GAIN 10
INT
E
R
F
ACE
L
O
G
IC
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
DB10
PD
VDD
DB0
DB1
DB2
DB7
DB6
DB3
DB4
DB5
12-BIT
AD5340
TOP VIEW
(Not to Scale)
DB8
DB9
DB11
LDAC
GND
BUF
VOUT
NC
VREF
CS
WR
GAIN
CLR
06
85
2-
008
Figure 7. AD5340 Functional Block Diagram
Figure 8. AD5340 Pin Configuration
Table 7. AD5340 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
DB10
Parallel Data Input.
2
DB11
Most Significant Bit of Parallel Data Input.
3
BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
4
VREF
Reference Input.
5
VOUT
Output of DAC. Buffered output with rail-to-rail operation.
6
NC
No Connect.
7
GND
Ground reference point for all circuitry on the part.
8
CS
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9
WR
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0 V to VREF or 0 V to 2 × VREF.
11
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
12
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
13
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
14
VDD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
15 to 24
DB0 to DB9
Ten Parallel Data Inputs.
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