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參數(shù)資料
| 型號(hào)： | AD5330BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8BIT SNGL VOUT 20-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.25mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
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AD5330/AD5331/AD5340/AD5341
Rev. A | Page 4 of 28
Parameter1
B Version2
Unit
Conditions/Comments
Min
Typ
Max
POWER REQUIREMENTS
VDD
2.5
5.5
V
IDD (Normal Mode)
DACs active and excluding load currents. Unbuffered
VDD = 4.5 V to 5.5 V
140
250
μA
Reference, VIH = VDD, VIL = GND
VDD = 2.5 V to 3.6 V
115
200
μA
IDD increases by 50 μA at VREF > VDD 100 mV.
In buffered mode, extra current is (5 + VREF/RDAC) μA,
where RDAC is the resistance of the resistor string.
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
0.2
1
μA
VDD = 2.5 V to 3.6 V
0.08
1
μA
1 See the Terminology section.
2 Temperature range: B Version: 40°C to +105°C; typical specifications are at 25°C.
3 Linearity is tested using a reduced code range: AD5330 (Code 8 to Code 255); AD5331 (Code 28 to Code 1023); AD5340/AD5341 (Code 115 to Code 4095).
4 DC specifications tested with output unloaded.
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization, not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
AC CHARACTERISTICS1
VDD = 2.5 V to 5.5 V. RL = 2 kΩ to GND, CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
B Version3
Unit
Conditions/Comments
Min
Typ
Max
Output Voltage Settling Time
AD5330
6
8
μs
scale to scale change (0x40 to 0xC0)
AD5331
7
9
μs
scale to scale change (0x100 to 0x300)
AD5340
8
10
μs
scale to scale change (0x400 to 0xC00)
AD5341
8
10
μs
scale to scale change (0x400 to 0xC00)
Slew Rate
0.7
V/μs
Major Code Transition Glitch Energy
6
nV/s
1 LSB change around major carry
Digital Feedthrough
0.5
nV/s
Multiplying Bandwidth
200
kHz
VREF = 2 V ± 0.1 V p-p; unbuffered mode
Total Harmonic Distortion
70
dB
VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1 Guaranteed by design and characterization, not production tested.
2 See the Terminology section.
3 Temperature range: B Version: 40°C to +105°C; typical specifications are at 25°C.
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