參數(shù)資料
型號: AD5330BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 11/28頁
文件大?。?/td> 0K
描述: IC DAC 8BIT SNGL VOUT 20-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 75
設(shè)置時間: 6µs
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1.25mW
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): 167k
產(chǎn)品目錄頁面: 782 (CN2011-ZH PDF)
AD5330/AD5331/AD5340/AD5341
Rev. A | Page 19 of 28
POWER-DOWN MODE
The AD5330/AD5331/AD5340/AD5341 have low power
consumption, dissipating only 0.35 mW with a 3 V supply and
0.7 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into power-
down mode, which is selected by taking Pin PD low.
When the PD pin is high, the DAC works normally with a
typical power consumption of 140 μA at 5 V (115 μA at 3 V).
In power-down mode, however, the supply current falls to
200 nA at 5 V (80 nA at 3 V) when the DAC is powered down.
Not only does the supply current drop, but the output stage
is also internally switched from the output of the amplifier,
making it open-circuit. This has the advantage that the output
is three-state while the part is in power-down mode and provides
a defined input condition for whatever is connected to the
output of the DAC amplifier. The output stage is illustrated in
.
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
VOUT
0
685
2-
0
40
Figure 39. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 μs for VDD = 5 V and 5 μs when
VDD = 3 V. This is the time from a rising edge on the PD pin to
when the output voltage deviates from its power-down voltage
(see
).
Table 9. AD5330/AD5331/AD5340 Truth Table1
CLR
LDAC
CS
WR
Function
1
X
No data transfer
1
X
1
No data transfer
0
X
Clear all registers
1
0
→1
Load input register
1
0
→1
Load input register and DAC register
1
0
X
Update DAC register
1 X = don’t care.
Table 10. AD5341 Truth Table1
CLR
LDAC
CS
WR
HBEN
Function
1
X
No data transfer
1
X
1
X
No data transfer
0
X
Clear all registers
1
0
→1
0
Load low byte input register
1
0
→1
1
Load high byte input register
1
0
→1
0
Load low byte input register and DAC register
1
0
→1
1
Load high byte input register and DAC register
1
0
X
Update DAC register
1 X = don’t care.
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